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參數(shù)資料
| 型號： | MC68HC11A1VFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 77/158頁 |
| 文件大小： | 503K |
| 代理商： | MC68HC11A1VFU2 |
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MC68HC11A8
TECHNICAL DATA
PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
MOTOROLA
8-7
8
PR1 and PR0 — Timer Prescaler Selects
These two bits may be read at any time but may only be written during initialization.
Writes are disabled after the first write or after 64 E cycles out of reset. If the MCU is
in special test or special bootstrap mode, then these two bits may be written any time.
These two bits specify the timer prescaler divide factor.
8.1.13 Timer Interrupt Flag Register 2 (TFLG2)
Timer interrupt flag register 2 is used to indicate the occurrence of timer system events
and, together with the TMSK2 register, allows the timer subsystems to operate in a
polled or interrupt driven system. For each bit in timer flag register 2 (TFLG2), there is
a corresponding bit in timer mask register 2 (TMSK2) in the same bit position. If the
enable bit is set each time the conditions for the corresponding flag are met, a hard-
ware interrupt sequence is requested as well as the flag bit being set.
The timer system status flags are cleared by writing a one to the bit positions corre-
sponding to the flag(s) which are to be cleared. Bit manipulation instructions would be
inappropriate for flag clearing because they are read-modify-write instructions. Even
though the instruction mask implies that the programmer is only interested in some of
the bits in the manipulated location, the entire location is actually read and rewritten
which may clear other bits in the register.
TOF — Timer Overflow
This bit is cleared by reset. It is set to one each time the 16-bit free-running counter
advances from a value of $FFFF to $0000. This bit is cleared by a write to the TFLG2
register with bit 7 set.
RTIF — Real Time Interrupt Flag
This bit is set at each rising edge of the selected tap point. This bit is cleared by a write
to the TFLG2 register with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
This bit is set when the count in the pulse accumulator rolls over from $FF to $00. This
bit is cleared by a write to the TFLG2 register with bit 5 set.
PR1
0
PR0
0
Prescaler
÷
1
÷
4
÷
8
÷
16
0
1
1
0
1
1
7
6
5
4
3
0
0
2
0
0
1
0
0
0
0
0
$
1
025
RESET
TOF
0
RTIF
0
PAOVF
0
PAIF
0
TFLG2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11A1VP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A1VP2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A8BCFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8BCFU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
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