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參數資料
| 型號： | MC68HC11A1VFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數： | 87/158頁 |
| 文件大小： | 503K |
| 代理商： | MC68HC11A1VFU2 |
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MC68HC11A8
TECHNICAL DATA
RESETS, INTERRUPTS, AND LOW POWER MODES
MOTOROLA
9-7
9
CSEL — A/D/EE Charge Pump Clock Source Select
This bit determines the clocking source for the on-chip A/D and EEPROM charge
pump. When this bit is zero, the MCU E clock drives the A/D system and the EEPROM
charge pump. When CSEL is one, on-chip separate R-C oscillators are enabled and
clock the systems at about 2 MHz. When running with an E clock below 1 MHz, CSEL
must be high to program or erase EEPROM. When operating below 750 kHz E clock
rate, CSEL should be high for A/D conversions. A delay of 10 milliseconds is required
after CSEL is turned on to allow the A/D system to stabilize.
IRQE — IRQ Edge/Level Sensitive
This bit may only be written under special circumstances as described above. When
this bit is clear, the IRQ pin is configured for level sensitive wired-OR operation (low
level) and when it is set, the IRQ pin is configured for edge-only sensitivity (falling edg-
es).
DLY — STOP Exit Turn-On Delay
This bit may only be written under special circumstances as described above. This bit
is set during reset and controls whether or not a relatively long turn-on delay will be
imposed before processing can resume after a STOP period. If an external clock
source is supplied this delay can be inhibited so that processing can resume within a
few cycles of a wake up from STOP mode. When DLY is set, a 4064 E clock cycle de-
lay is imposed to allow oscillator stabilization and when DLY is clear, this delay is by-
passed.
CME — Clock Monitor Enable
This control bit may be read or written at any time and controls whether or not the in-
ternal clock monitor circuit will trigger a reset sequence when a slow or absent system
clock is detected. When it is clear, the clock monitor circuit is disabled and when it is
set, the clock monitor circuit is enabled. Systems operating at or below 200 kHz should
not use the clock monitor function. Reset clears the CME bit.
Bit 2 — Not Implemented
This bit always reads zero.
CR1 and CR0 — COP Timer Rate Selects
These bits may only be written under special circumstances as described above. Re-
fer to
Table 9-1
for the relationship between CR1:CR0 and the COP timeout period.
9.2 Interrupts
When an external or internal (hardware) interrupt occurs, the interrupt is not serviced
until the current instruction being executed is completed. Until the current instruction
is complete, the interrupt is considered pending. After completion of current instruction
execution, unmasked interrupts may be serviced in accordance with an established
fixed hardware priority circuit; however, one l-bit related interrupt source may be dy-
namically elevated to the highest I bit priority position in the hierarchy (see
9.2.5 High-
est Priority I Interrupt Register (HPRIO)
).
Seventeen hardware interrupts and one software interrupt (excluding reset type inter-
rupts) can be generated from all of the possible sources. The interrupts can be divided
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相關代理商/技術參數 |
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| MC68HC11A1VP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
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| MC68HC11A8BCFU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
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