- 您現在的位置：買賣IC網 > PDF目錄371048 > MC68HC11A8BCFU2 (MOTOROLA INC) HCMOS Single-Chip Microcontroller PDF資料下載
參數資料
| 型號： | MC68HC11A8BCFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數： | 61/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8BCFU2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
MC68HC11A8
TECHNICAL DATA
SERIAL PERIPHERAL INTERFACE
MOTOROLA
6-3
6
6.3 Functional Description
Figure 6-2
shows a block diagram of the serial peripheral interface circuitry. When a
master device transmits data to a slave device via the MOSI line, the slave device re-
sponds by sending data to the master device via the master’s MISO line. This implies
full duplex transmission with both data out and data in synchronized with the same
clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates
the need for separate transmit-empty and receiver-full status bits. A single status bit
(SPIF) is used to signify that the l/O operation has been completed.
The SPI is double buffered on read, but not on write. If a write is performed during data
transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This
condition will cause the write collision (WCOL) status bit in the SPSR to be set. After
a data byte is shifted, the SPIF flag of the SPSR is set.
Figure 6-2 Serial Peripheral Interface Block Diagram
In the master mode, the SCK pin is an output. It idles high or low, depending on the
CPOL bit in the SPCR, until data is written to the shift register, at which point eight
clocks are generated to shift the eight bits of data and then SCK goes idle again.
In a slave mode, the slave start logic receives a logic low at the SS pin and a clock
input at the SCK pin. Thus, the slave is synchronized with the master. Data from the
master is received serially at the slave MOSI line and loads the 8-bit shift register. After
the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. During
a write cycle, data is written into the shift register, then the slave waits for a clock train
from the master to shift the data out on the slave’s MISO line.
PIN
CONTROL
LOGIC
MISO
PD2
DIVIDER
CLOCK
LOGIC
SPI STATUS (SPSR)
SPI BLOCK DIAGRAM
S
S
SPI CONTROL (SPCR)
D
M
C
C
S
S
S
W
M
8-BIT SHIFT REGISTER
READ DATA BUFFER
MSB
LSB
CLOCK
M
M
S
S
M
S
SELECT
÷
2
÷
4
÷
16
÷
32
INTERNAL
MCU SYSTEM
CLOCK
SPI CONTROL
S
S
MOSI
PD3
SCK
PD4
SS
PD5
M
S
D
MSTR
SPE
SPIE
SPI CLOCK (MSTR = 1)
8
SPI
INTERRUPT
相關PDF資料 |
PDF描述 |
|---|---|
| MC68HC11A8BCP2 | HCMOS Single-Chip Microcontroller |
| MC68HC11A8BMP2 | HCMOS Single-Chip Microcontroller |
| MC68HC11A8BVP2 | HCMOS Single-Chip Microcontroller |
| MC68HC11A1CFN2 | HCMOS Single-Chip Microcontroller |
| MC68HCP11A1CFN2 | HCMOS Single-Chip Microcontroller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68HC11A8BCP2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8BMP2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8BVP2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8FN | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A8FN1 | 制造商:Motorola Inc 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。