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參數資料
| 型號： | MC68HC11A8VCFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數： | 21/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8VCFU2 |
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MC68HC11A8
TECHNICAL DATA
SIGNAL DESCRIPTIONS AND OPERATING MODES
MOTOROLA
2-5
2
2.1.11.1 Port A
Port A may be configured for: three input capture functions (IC1, IC2, IC3), four output
compare functions (OC2, OC3, OC4, OC5), and either a pulse accumulator input (PAI)
or a fifth output compare function (OC1). Refer to
8.1 Programmable Timer
for addi-
tional information.
Any port A pin that is not used for its alternate timer function may be used as a general-
purpose input or output line.
2.1.11.2 Port B
While in single-chip operating modes, all of the port B pins are general-purpose output
pins. During MCU reads of this port, the level sensed at the input side of the port B
output drivers is read. Port B may also be used in a simple strobed output mode where
an output pulse appears at the STRB signal each time data is written to port B.
When in expanded multiplexed operating modes, all of the port B pins act as high order
address output signals. During each MCU cycle, bits 8 through 15 of the address are
output on the PB0-PB7 lines respectively.
2.1.11.3 Port C
While in single-chip operating modes, all port C pins are general-purpose input/output
pins. Port C inputs can be latched by providing an input transition to the STRA signal.
Port C may also be used in full handshake modes of parallel l/O where the STRA input
and STRB output act as handshake control lines.
When in expanded multiplexed operating modes, all port C pins are configured as mul-
tiplexed address/data signals. During the address portion of each MCU cycle, bits 0
through 7 of the address are output on the PC0-PC7 lines. During the data portion of
each MCU cycle (E high), pins 0 through 7 are bidirectional data signals (D0-D7). The
direction of data at the port C pins is indicated by the R/W signal.
2.1.11.4 Port D
Port D pins 0-5 may be used for general-purpose l/O signals. Port D pins alternately
serve as the serial communications interface (SCI) and serial peripheral interface
(SPI) signals when those subsystems are enabled.
Pin PD0 is the receive data input (RxD) signal for the serial communication interface
(SCI).
Pin PD1 is the transmit data output (TxD) signal for the SCI.
Pins PD2 through PD5 are dedicated to the SPI. PD2 is the master-in-slave-out (MI-
SO) signal. PD3 is the master-out-slave-in (MOSI) signal. PD4 is the serial clock
(SCK) signal and PD5 is the slave select (SS) input.
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