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參數資料
| 型號： | MC68HC11K1MFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數： | 54/80頁 |
| 文件大小： | 420K |
| 代理商： | MC68HC11K1MFN2 |
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MOTOROLA
54
M68HC11 K Series
MC68HC11KTS/D
RE —Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
RWU —Receiver Wakeup Control
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
SBK —Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
TDRE —Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR1 and then writing to SCDR.
0 = SCDR busy
1 = SCDR empty
TC —Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
the TC flag by reading SCSR1 and then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF —Receive Data Register Full Flag
RDRF is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR1 and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE —Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1
and then reading SCDR.
0 = RxD line is active
1 = RxD line is idle
OR —Overrun Error Flag
OR is set if a new character is received before a previously received character is read from SCDR. Clear
the OR flag by reading SCSR1 and then reading SCDR.
0 = No overrun
1 = Overrun detected
NF —Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading
SCSR1 and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE —Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR1
and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
SCSR1
—SCI Status Register 1
$0074
Bit 7
TDRE
1
6
5
4
3
2
1
Bit 0
PF
0
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
RESET:
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