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參數資料
| 型號： | MC68HC16Y1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Modular Microcontroller(16位模塊化微控制器) |
| 中文描述： | 16位微控制器模塊（16位模塊化微控制器） |
| 文件頁數： | 107/122頁 |
| 文件大小： | 749K |
| 代理商： | MC68HC16Y1 |
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MC68HC16Y1
MC68HC16Y1TS/D
MOTOROLA
107
7.2.3 SPI Operation
The SPI operates in either master or slave mode. Master mode is used when the SPI originates data
transfers. Slave mode is used when an external device initiates serial transfers to the SPI. Switching
between the modes is controlled by MSTR in SPCR. Prior to entering either mode, appropriate MCCI
and SPI registers must be properly initialized.
In master mode, transmission parameters are set by writing to SPCR, the SPI is enabled by setting
SPE, then operation is initiated by writing data to SPDR. In slave mode, operation proceeds in response
to SS signal assertion by an external bus master. Slave operation is similar to that of master mode.
Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus
master supplies the clock signal (SCK) to time the transfer of data. Four possible combinations of clock
phase and polarity may be specified by means of the CPHA and CPOL bits in SPCR. Data can be trans-
ferred either LSB or MSB first, depending on the value of the LSBF bit in SPCR. The number of bits
transferred per command defaults to eight, but may be set to 16 bits by setting the field in SPCR.
When the SPI finishes a transmission, it sets the SPIF flag, clears SPE and stops. If the SPIE bit in
SPCR is set, an interrupt request is generated when SPIF is set.
Although the SPI inherently supports multimaster operation, no special arbitration mechanism is provid-
ed. A mode fault flag (MODF) indicates a request for SPI master arbitration — system software must
provide arbitration.
Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the system. If needed,
the WOMP bit in SPCR can be set to provide wired-OR open-drain outputs. An external pull-up resistor
should be used on each output line. WOMP affects all SPI pins regardless of whether they are assigned
to the SPI or used as general-purpose I/O.
7.3 Serial Communication Interface
There are two identical independent SCI systems, SCIA and SCIB, in the MCCI. Each is a full-duplex
universal asynchronous receiver transmitter (UART). Each SCI system is fully compatible with the SCI
systems found on other Motorola devices, such as the M68HC11 and M68HC05 Families. The following
discussions apply to both SCIA and SCIB — differences in register addresses and pin names are noted.
7.3.1 SCI Pins
Two unidirectional transmit data pins, TXDA and TXDB, and two unidirectional receive data pins, RXDA
and RXDB, are associated with each SCI. Each pin can be used by the associated SCI or for general-
purpose I/O.
SCI pins and their functions are shown below.
7.3.2 SCI Registers
The SCI programming model includes the MCCI global and pin control registers, and eight SCI regis-
ters. Each of the two SCI units contains two SCI control registers, one status register, and one data reg-
ister.
All registers may be read or written at any time by the CPU. Rewriting the same value to any SCI register
does not disrupt operation; however, writing a different value into an SCI register when the SCI is run-
ning may disrupt operation. To change register values, the receiver and transmitter should be disabled
with the transmitter allowed to finish first. The status flags in register SCSR may be cleared at any time.
Pin Names
Receive Data
A and B
Transmit Data
A and B
Mnemonics
RXDA, RXDB
Mode
Function
Receiver Disabled
Receiver Enabled
Transmitter Disabled
Transmitter Enabled
General-Purpose I/O
Serial Data Input to SCI
General-Purpose I/O
Serial Data Output from SCI
TXDA, TXDB
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| MC68HC16Z1CAG20 | 功能描述:16位微控制器 - MCU 16 BIT MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
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