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| 型號(hào)： | MC68HC901 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | 多功能外設(shè) |
| 文件頁(yè)數(shù)： | 59/73頁(yè) |
| 文件大小： | 274K |
| 代理商： | MC68HC901 |
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Electrical Characteristics
8-6
MC68HC901 USER’S MANUAL
MOTOROLA
28
Receiver Ready (RR) Delay from Rising RC
—
600
ns
29
Transmitter Ready (TR) Delay from Rising TC
—
600
ns
30
TxO (A or B) Low from Rising Edge of CS or DS (Reset Time)
—
450
ns
31
3
Timer Output (TxO) Valid from Falling t
clk
that Causes Timeout
—
2 t
clk
+ 300
ns
32
Timer Clock (t
clk
) Low Time
110
—
ns
33
Timer Clock (t
clk
) High Time
110
—
ns
34
Timer Clock (t
clk
) Cycle Time
250
1000
ns
35
RESET Low Time
2
—
μ
s
36
Delay to Falling IRQ from Ix Active Transition
—
380
ns
37
Transmitter Interrupt Delay from Falling Edge of TC
—
550
ns
38
Receiver Interrupt Delay from Rising Edge of RC (Buffer Full)
—
800
ns
39
Receiver Interrupt Delay from Falling Edge of RC (Error)
—
800
ns
40
SI Setup Time from Rising Edge of RC (Divide by 1 Only)
80
—
ns
41
SI Hold Time from Rising Edge of RC (Divide by 1 Only)
350
—
ns
42
SO Data Valid from Falling Edge of TC (Divide by 1 Only)
—
440
ns
43
TC Low Time
500
—
ns
44
TC High Time
500
—
ns
45
TC Cycle Time
1.05
∞
μ
s
46
RC Low Time
500
—
ns
47
RC High Time
500
—
ns
48
RC Cycle Time
1.05
∞
μ
s
49
3
CS, IACK, DS Width Low
—
80
t
cyc
50
SO Data Valid from Falling Edge of TC (Divide by 16 Only)
—
490
ns
NOTES: 1.
If the setup time is not met, CS will not be recognized until the next falling clock.
If this setup time is met (for consecutive cycles), the minimum hold-off time of one clock cycle will be
obtained. If not met, the hold-off time will be two clock cycles.
t
cyc
refers to the clock signal applied to the MFP CLK input pin. t
clk
regardless of whether that signal comes from the XTAL1/XTAL2 crystal clock inputs or the TAI or TBI timer
inputs.
CS is latched internally, therefore if specifications 1 and 24 are met, then CS may be negated before the
falling clock and still initiate a bus cycle.
Although CS and DTACK are synchronized with the clock, the data out during a read cycle is
asynchronous to the clock, relying only on CS for timing.
2.
3.
refers to the timer clock signal,
4.
5.
NUM
CHARACTERISTIC
MIN
MAX
UNIT
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