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參數資料
| 型號： | MC68HC901FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 15/73頁 |
| 文件大?。?/td> | 274K |
| 代理商： | MC68HC901FN |
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Signal Description
2-2
MC68HC901 USER’S MANUAL
MOTOROLA
2.2 CLOCK (CLK)
The clock input is a single-phase TTL-compatible signal used for internal timing. This input
must conform to minimum pulse width times. The clock is not necessarily the system clock
in frequency or phase.
2.3 DATA BUS (D7–D0)
This three-state bidirectional bus is used to transmit data to or receive data from the MFP
internal registers during a processor read or write cycle, respectively. During an interrupt
acknowledge cycle, the data bus is used to pass a vector number to the processor. The MFP
must be located on data bus lines D7–D0 when used with either the MC68000 series of
microprocessors and on data lines D31–D24 when used with the MC68020 microprocessor,
if vectored interrupts are to be used.
2.4 ASYNCHRONOUS BUS CONTROL
Asynchronous data transfers are controlled by chip select, data strobe, read/write, and data
transfer acknowledge. The register select lines, RS5–RS1, select an internal MFP register
for a read or write operation. The reset line initializes the MFP registers and the internal
control signals.
2.4.1 Chip Select (CS)
This active low input activates the MFP for internal register access. CS and IACK must not
be asserted at the same time.
2.4.2 Data Strobe (DS)
This active low input is part of the internal chip select and interrupt acknowledge functions.
2.4.3 Read/Write (R/W)
This input defines the current bus cycle as a read (high) or a write (low) cycle.
2.4.4 Data Transfer Acknowledge (DTACK)
This active low, three-state output signals the completion of the operation phase of a bus
cycle to the processor. If the bus cycle is a process read, the MFP asserts DTACK to indicate
that the information on the data bus is valid. If the bus cycle is a processor write to the MFP,
DTACK acknowledges the acceptance of the data by the MFP. DTACK will be asserted only
by a MFP that has CS or IACK (and IEI) asserted.
2.5 REGISTER SELECT BUS (RS1–RS5)
The register select bus selects an internal MFP register during a read or write operation.
2.6 RESET (RESET)
This active low input will initialize the MFP during powerup or in response to a total system
reset. Refer to
Section 3.3 Reset Operation
for further information.
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