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參數資料
| 型號： | MC68HC901FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 36/73頁 |
| 文件大?。?/td> | 274K |
| 代理商： | MC68HC901FN |
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MOTOROLA
MC68HC901 USER’S MANUAL
5-1
SECTION 5
GENERAL PURPOSE INPUT/OUTPUT PORT
The general purpose input/output (I/O) port (GPIP) provides eight I/O lines (I0 through I7)
that may be operated as either inputs or outputs under software control. In addition, these
lines may optionally generate an interrupt on either a positive transition or a negative
transition of the input signal. The flexibility of the GPIP allows it to be configured as an 8-bit
I/O port or for bit I/O. Since interrupts are enabled on a bit-by-bit basis, a subset of the GPIP
could be programmed as handshake lines or the port could be connected to as many as
eight external interrupt sources, which would be prioritized by the MFP interrupt controller
for the interrupt service.
5.1 GPIP CONTROL REGISTERS
The GPIP is programmed via three control registers. These registers control the data
direction, provide user access to the port, and specify the active edge for each bit of the
GPIP which will produce an interrupt. These registers are described in detail in the following
paragraphs.
5.1.1 General Purpose I/O Data Register (GPDR)
The general purpose I/O data register is used to input data from or output data to the port.
When data is written to the GPDR, those pins which are defined as inputs will remain in the
high-impedance state. Pins which are defined as outputs will assume the state (high or low)
of their corresponding bit in the data register. When the GPDR is read, data will be passed
directly from the bits of the data register for pins which are defined as outputs. Data from
pins defined as inputs will come from the input buffers.
GPIP7-GPIP0 – General Purpose I/O Port
0 = Cleared.
1 = Set.
5.1.2 Active Edge Register (AER)
The active edge register (AER) allows each of the GPIP lines to produce an interrupt on
either a one-to-zero or a zero-to-one transition. Writing a zero to the appropriate edge bit of
GPDR REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
GPIP7
GPIP6
GPIP5
GPIP4
GPIP3
GPIP2
GPIP1
GPIP0
RESET
0
0
0
0
0
0
0
0
ADDR
$01
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