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參數(shù)資料
型號: MC74ACT109
廠商: ON SEMICONDUCTOR
英文描述: DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
中文描述: 雙JK上升沿觸發(fā)器
文件頁數(shù): 2/6頁
文件大小: 197K
代理商: MC74ACT109
MC74AC109 MC74ACT109
5-2
FACT DATA
SD
K
CP
J
CD
Q
Q
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
LOGIC DIAGRAM
(one half shown)
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±
20
V
DC Output Voltage (Referenced to GND)
V
DC Input Current, per Pin
mA
DC Output Sink/Source Current, per Pin
±
50
mA
DC VCC or GND Current per Output Pin
Storage Temperature
±
50
mA
–65 to +150
°
C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
AC
ACT
2.0
5.0
6.0
V
4.5
5.0
5.5
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
0
VCC
V
AC Devices except Schmitt Inputs
VCC @ 3.0 V
VCC @ 4.5 V
VCC @ 5.5 V
VCC @ 4.5 V
VCC @ 5.5 V
150
tr, tf
Input Rise and Fall Time (Note 1)
40
ns/V
25
tr, tf
Input Rise and Fall Time (Note 2)
ACT Devices except Schmitt Inputs
10
ns/V
8.0
TJ
TA
IOH
IOL
Junction Temperature (PDIP)
140
°
C
Operating Ambient Temperature Range
–40
25
85
°
C
Output Current — High
–24
mA
Output Current — Low
24
mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
相關(guān)PDF資料
PDF描述
MC74AC109D DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC74AC109N DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC74ACT109N DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC74ACT10D TRIPLE 3-INPUT NAND GATE
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