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參數(shù)資料
| 型號(hào)： | MC74ACT109 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP |
| 中文描述： | 雙JK上升沿觸發(fā)器 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 197K |
| 代理商： | MC74ACT109 |
MC74AC109 MC74ACT109
5-3
FACT DATA
DC CHARACTERISTICS
Symbol
Parameter
(V)
74AC
74AC
Unit
Conditions
VCC
TA = +25
°
C
TA =
–40
°
C to +85
°
C
Typ
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
VOUT = 0.1 V
or VCC – 0.1 V
V
VIL
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
VOUT = 0.1 V
or VCC – 0.1 V
V
VOH
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
IOUT = –50
μ
A
V
V
*VIN = VIL or VIH
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
–12 mA
–24 mA
–24 mA
IOH
VOL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
IOUT = 50
μ
A
V
V
*VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
IOL
IIN
Maximum Input
Leakage Current
5.5
±
0.1
±
1.0
μ
A
VI = VCC, GND
IOLD
Minimum Dynamic
Output Current
5.5
75
mA
VOLD = 1.65 V Max
IOHD
5.5
–75
mA
VOHD = 3.85 V Min
ICC
Maximum Quiescent
Supply Current
5.5
4.0
40
μ
A
VIN = VCC or GND
* All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
AC CHARACTERISTICS
(For Figures and Waveforms — See Section 3)
Symbol
Parameter
(V)
74AC
74AC
Unit
No.
VCC*
TA = +25
°
C
CL = 50 pF
TA = –40
°
C
to +85
°
C
CL = 50 pF
Fig.
Min
Typ
Max
Min
Max
fmax
Maximum Clock
Frequency
3.3
5.0
125
150
100
125
MHz
3-3
tPLH
Propagation Delay
CPn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
3.3
5.0
4.0
2.5
13.5
10.0
3.5
2.0
16.0
10.5
ns
3-6
tPHL
3.3
5.0
3.0
2.0
14.0
10.0
3.0
1.5
14.5
10.5
ns
3-6
tPLH
3.3
5.0
3.0
2.5
12.0
9.0
2.5
2.0
13.0
10.0
ns
3-6
tPHL
3.3
5.0
3.0
2.0
12.0
9.5
3.0
2.0
13.5
10.5
ns
3-6
* Voltage Range 3.3 V is 3.3 V
±
0.3 V.
Voltage Range 5.0 V is 5.0 V
±
0.5 V.
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| MC74AC109N | DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP |
| MC74ACT109N | DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74ACT109D | 制造商:ON Semiconductor 功能描述:Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SOIC Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74ACT109DR2 | 制造商:ON Semiconductor 功能描述:Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74ACT109DT | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop |
| MC74ACT109DTR2 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop |
| MC74ACT109M | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop |
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