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參數(shù)資料
型號: MC74ACT109D
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
中文描述: ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝: PLASTIC, SOIC-16
文件頁數(shù): 5/6頁
文件大小: 197K
代理商: MC74ACT109D
MC74AC109 MC74ACT109
5-5
FACT DATA
AC CHARACTERISTICS
(For Figures and Waveforms — See Section 3)
Symbol
Parameter
(V)
74ACT
74ACT
Unit
No.
VCC*
TA = +25
°
C
CL = 50 pF
TA = –40
°
C
to +85
°
C
CL = 50 pF
Fig.
Min
Typ
Max
Min
Max
fmax
Maximum Clock
Frequency
5.0
145
125
MHz
3-3
tPLH
Propagation Delay
CPn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
5.0
4.0
11.0
3.5
13.0
ns
3-6
tPHL
5.0
3.0
10.0
2.5
11.5
ns
3-6
tPLH
5.0
2.5
9.5
2.0
10.5
ns
3-6
tPHL
5.0
2.5
10.0
2.0
11.5
ns
3-6
* Voltage Range 5.0 V is 5.0 V
±
0.5 V.
AC OPERATING REQUIREMENTS
Symbol
Parameter
(V)
74ACT
74ACT
Unit
No.
VCC*
TA = +25
°
C
CL = 50 pF
TA = –40
°
C
to +85
°
C
CL = 50 pF
Fig.
Typ
Guaranteed Minimum
ts
Set-up Time, HIGH or LOW
Jn or Kn to CPn
Hold Time, HIGH or LOW
Jn or Kn to CPn
Pulse Width
CPn or CDn or SDn
Recovery TIme
CDn or SDn to CP
5.0
2.0
2.5
ns
3-9
th
5.0
2.0
2.0
ns
3-9
tw
5.0
5.0
6.0
ns
3-6
trec
5.0
0
0
ns
3-9
* Voltage Range 5.0 V is 5.0 V
±
0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
35
pF
VCC = 5.0 V
相關PDF資料
PDF描述
MC74AC109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC74ACT109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC74AC109D DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC74AC109N DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MC74ACT109N DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
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