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參數資料
| 型號： | MC74HC173N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 3-State D Flip-Flop with Common Clock and Reset |
| 中文描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 2/6頁 |
| 文件大小： | 225K |
| 代理商： | MC74HC173N |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
±
75
Power Dissipation in Still Air
mA
Plastic DIP
mW
750
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
0
400
VCC = 6.0 V
Symbol
Parameter
Test Conditions
V
– 55 to
25 C
85 C
4.2
4.2
VCC
125 C
4.2
6.0
Unit
VIL
Maximum Low–Level Input
Vout = 0.1 V or VCC – 0.1 V
2.0
0.3
0.3
0.3
Minimum High–Level Output
2.0
1.9
1.9
1.9
V
7.8 mA
5.48
5.34
5.20
V
VOL
Maximum Low–Level Output
Vin = VIH or VIL
|Iout|
6.0
2.0
6.0
0.1
0.1
0.1
0.1
0.1
0.1
6.0 mA
0.26
0.33
0.40
V
Vin = VIL or VIH
Vout = VCC or GND
4.5
Leakage Current
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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