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參數(shù)資料
| 型號： | MC74HC20AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-Input NAND Gate |
| 中文描述： | HC/UH SERIES, DUAL 4-INPUT NAND GATE, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 132K |
| 代理商： | MC74HC20AN |
MC74HC20A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: –7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
V
450
mW
– 65 to + 150
C
C
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
400
(Figure 1)
VCC = 3.0 V
0
0
1000
600
500
ns
VCC
25 C
85 C
Guaranteed Limit
5.2 mA
3.15
– 55 to
3.98
5.48
Minimum High–Level Input
Voltage
6.0
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20
μ
A
4.5
0.9
1.8
3.15
3.15
Voltage
|Iout|
20
μ
A
3.0
0.9
0.9
Voltage
|Iout|
20
μ
A
4.5
1.9
4.4
3.70
5.20
4.4
4.4
V
Vin = VIH or VIL
|Iout|
|Iout|
|Iout|
4.5
6.0
3.84
5.34
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
(Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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