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參數(shù)資料
| 型號： | MC74HC20AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-Input NAND Gate |
| 中文描述： | HC/UH SERIES, DUAL 4-INPUT NAND GATE, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大小： | 132K |
| 代理商： | MC74HC20AN |
MC74HC20A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
Voltage
|Iout|
20
μ
A
0.1
0.1
4.5
Vin = VCC or GND
μ
A
5.2 mA
0.26
0.26
0.1
0.40
0.40
Vin = VIH or VIL
|Iout|
|Iout|
|Iout|
4.5
6.0
0.33
0.33
Current (per Package)
Maximum Quiescent Supply
A
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
(CL = 50 pF, Input tr = tf = 6 ns)
VCC
V
Guaranteed Limit
6.0
45
15
– 55 to
30
13
23
6.0
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
3.0
19
60
75
tTHL
(Figures 1 and 2)
3.0
75
40
16
55
ns
CPD
Power Dissipation Capacitance (Per Gate)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
26
pF
Figure 1. Switching Waveforms
INPUT
A, B, C, OR D
OUTPUT Y
tf
tr
VCC
GND
tPHL
tPLH
90%
50%
10%
tTLH
tTHL
90%
50%
10%
A
B
C
D
Y
EXPANDED LOGIC DIAGRAM
(1/2 OF THE DEVICE)
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 2. Test Circuit
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