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參數(shù)資料
| 型號： | MC74HC597N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch |
| 中文描述： | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 291K |
| 代理商： | MC74HC597N |
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1995
10/95
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High–Performance Silicon–Gate CMOS
The MC54/74HC597A is identical in pinout to the LS597. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of an 8–bit input latch which feeds parallel data to an
8–bit shift register. Data can also be loaded serially (see Function Table).
The HC597A is similar in function to the HC589A, which is a 3–state
device.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 516 FETs or 129 Equivalent Gates
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
15
1
2
3
4
5
6
7
12
11
13
10
SA
A
B
C
D
E
F
G
H
LATCH CLOCK
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
RESET
PARALLEL
DATA
INPUTS
INPUT
LATCH
SHIFT
REGISTER
PIN 16 = VCC
PIN 8 = GND
9
QH
SERIAL
DATA
OUTPUT
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
LATCH CLOCK
SERIAL SHIFT/
PARALLEL LOAD
SA
A
VCC
QH
RESET
SHIFT CLOCK
E
D
C
B
GND
H
G
F
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
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