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參數(shù)資料
| 型號(hào)： | MC74HC688 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Equality Comparator |
| 中文描述： | 8位比較平等 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 202K |
| 代理商： | MC74HC688 |
MC54/74HC688
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 3)
4.5
42
63
6.0
20
53
31
tTLH,
Maximum Output Transition Time, Any Output
2.0
75
26
110
ns
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
95
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
30
pF
SWITCHING WAVEFORMS
CASCADE
INPUT
tf
tr
VCC
GND
10%
950%
tPHL
tPLH
10%
50%
tTHL
tTLH
VCC
GND
50%
INPUT
A OR B
tPLH
tPHL
50%
A = B
OUTPUT
VALID
VALID
Figure 1.
Figure 2.
A = B
OUTPUT
TEST CIRCUITS
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
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