- 您現在的位置：買賣IC網 > PDF目錄371067 > MC74HC75 (Motorola, Inc.) Dual 2-Bit Transparent Latch PDF資料下載
參數資料
| 型號： | MC74HC75 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 2-Bit Transparent Latch |
| 中文描述： | 雙路2位透明鎖存器 |
| 文件頁數： | 3/5頁 |
| 文件大小： | 172K |
| 代理商： | MC74HC75 |
MC74HC75
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 5)
4.5
6.0
25
21
38
32
tPLH,
Maximum Propagation Delay, D to Q
2.0
110
140
31
26
165
ns
tPHL
(Figures 2 and 5)
4.5
6.0
29
25
44
38
tPLH,
Maximum Propagation Delay, Latch Enable to
Q
2.0
125
155
36
31
190
ns
tTHL
(Figures 3 and 5)
4.5
6.0
15
13
22
19
Cin
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
19
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Latch)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
35
pF
Symbol
Parameter
V
25 C
Unit
(Figure 4)
4.5
20
85 C
125 C
30
ns
6.0
5
25
(Figure 4)
4.5
16
6
24
7
ns
6.0
400
400
20
400
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
相關PDF資料 |
PDF描述 |
|---|---|
| MC74HC75D | Dual 2-Bit Transparent Latch |
| MC74HC75N | Dual 2-Bit Transparent Latch |
| MC74HCT00A | Quad 2-Input NAND Gate with LSTTL-Compatible Inputs |
| MC74HCT04T | With LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS |
| MC74HCT138A | 1-of-8 Decoder/Demultiplexer with LSTTL Compatible Inputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC74HC75D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC75F | 制造商:ON Semiconductor 功能描述: |
| MC74HC75FL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC75N | 制造商:Motorola Inc 功能描述: |
| MC74HC85 WAF | 制造商:ON Semiconductor 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。