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參數(shù)資料
| 型號： | MC88LV926DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CMOS PLL 68060 CLOCK DRIVER |
| 中文描述： | LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 108K |
| 代理商： | MC88LV926DW |
MC88LV926
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
6
Application Notes
1. Several specifications can only be measured when the
MC88LV926 is in phase–locked operation. It is not
possible to have the part in phase–lock on ATE
(automated test equipment). Statistical characterization
techniques were used to guarantee those specifications
which cannot be measured on the ATE. MC88LV926 units
were fabricated with key transistor properties intentionally
varied to create a 14 cell designed experimental matrix. IC
performance was characterized over a range of transistor
properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area.
Response Surface Modeling (RSM) techniques were
used to relate IC performance to the CMOS transistor
properties over operation voltage and temperature. IC
performance to each specification and fab variation were
used in conjunction with Yield Surface Modeling
(YSM
) methodology to set performance limits of ATE
testable specifications within those which are to be
guaranteed by statistical characterization. In this way, all
units passing the ATE test will meet or exceed the
non–tested specifications limits.
2. A 470K
resistor tied to either Analog VCC or Analog
GND, as shown in Figure 2., is required to ensure no jitter
is present on the MC88LV926 outputs. This technique
causes a phase offset between the SYNC input and the
Q0 output, measured at the pins. The tPD spec describes
how this offset varies with process, temperature, and
voltage. The specs were arrived at by measuring the
phase relationship for the 14 lots described in note 1 while
the part was in phase–locked operation. The actual
measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase
measurements were made at 1.5V. See Figure 2. for a
graphical description.
3. Two specs (tRISE/FALL and tPULSE Width 2X_Q output,
see AC Specifications) guarantee that the MC88LV926
meets the 33MHz and 66MHz 68060 P–Clock input
specification.
Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present
When a 470K
Resistor Is Tied to VCC or Ground
470K
REFERENCE
RESISTOR
EXTERNAL
LOOP FILTER
330
0.1
μ
F
ANALOG GND
RC1
R2
C1
WITH THE 470K
RESISTOR TIED IN THIS FASHION THE TPD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
SYNC INPUT
Q0 OUTPUT
2.25ns
OFFSET
3V
5V
tPD = 2.25ns
±
1.0ns (TYPICAL VALUES)
SYNC INPUT
Q0 OUTPUT
–0.8ns
OFFSET
3V
5V
470K
REFERENCE
RESISTOR
330
0.1
μ
F
ANALOG GND
ANALOG VCC
R2
C1
WITH THE 470K
RESISTOR TIED IN THIS FASHION THE TPD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
tPD = –0.80ns
±
0.30ns
RC1
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