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參數資料
| 型號： | MC92053 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 2/6頁 |
| 文件大?。?/td> | 45K |
| 代理商： | MC92053 |
Motorola
MC92053
2
Figure 2. Framer Block Diagram
General Description
The MC92053 implements four copies of the TC sublay-
er of the DAVIC asymmetrical FTTC PHY specification
for network devices. The MC92053 key functional
blocks are described in the paragraphs which follow.
Tx UTOPIA Interface
The Transmit UTOPIA interface accepts ATM cells from
the ATM layer according to the UTOPIA Level 2 speci-
fication. Each cell is stored in one of the four transmit
cell FIFO’s. This block uses TXCLK provided by the
ATM layer. The FIFO’s are used for rate adaptation be-
tween TXCLK (the UTOPIA interface clock) and the de-
vice clock.
Rx UTOPIA Interface
The receive UTOPIA interface reads ATM cells from the
four receive cell FIFO’s and transfers them to the ATM
layer according to the ATM Forum UTOPIA Level 2
specification. This block uses RXCLK provided by the
ATM layer. The FIFO is used for rate adaptation be-
tween RXCLK (the UTOPIA interface clock) and the de-
vice clock.
Microprocessor Interface
The microprocessor interface is an 8-bit generic slave
interface. It is used for initializing the internal registers
and reading status registers and counters.
JTAG
The MC92053 provides JTAG boundary scan.
Framers
Each of the four framers performs the TC functions for
a single user. The blocks contained in a framer are
shown in Figure 2 and are described in the paragraphs
which follow.
Tx Cell Functions
The transmit cell functions block reads ATM cells from
a transmit cell FIFO. If there are no cells available when
a downstream frame should be transmitted, the cell
functions block generates an idle cell. It calculates the
HEC value based on the ATM header of each cell and
inserts it in the fifth octet of the cell. This block also ran-
domizes the payload of the ATM cells according to
ITU-T Recommendation I.432.
A count of the cells transferred from the transmit cell
FIFO is maintained.
Data Link Insertion Block
The data link insertion block provides direct serial ac-
cess to the data link bytes of the downstream frame
headers. The data link stream for the downstream
frames is optionally inserted using an output clock pin
and an input data pin. The device ID to which the data
link stream is destined is programmable.
Framing
Inter-
leaver
Random-
izer
Tx
PMD
I/F
Reed-
Solomon
Decoder
Deran-
domizer
Rx
PMD
I/F
Reed-
Solomon
Encoder
Tx Cell
Functions
Data
Link
Insertion
Reed-
Solomon
Encoder
Random-
izer
Frame
Header
Interpretation
Rx Cell
Functions
Data
Link
Extraction
Frame
Header
Generation
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