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MCF5272 User’s Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
9.3
9.4
9.5
9.5.1
9.5.2
9.6
9.7
9.8
9.9
9.10
9.10.1
9.10.2
9.10.3
Interface to SDRAM Devices............................................................................. 9-4
SDRAM Banks, Page Hits, and Page Misses..................................................... 9-6
SDRAM Registers .............................................................................................. 9-6
SDRAM Configuration Register (SDCR) ...................................................... 9-6
SDRAM Timing Register (SDTR)................................................................. 9-8
Auto Initialization............................................................................................... 9-9
Power-Down and Self-Refresh........................................................................... 9-9
Performance...................................................................................................... 9-10
Solving Timing Issues with SDCR[INV]......................................................... 9-13
SDRAM Interface............................................................................................. 9-15
SDRAM Read Accesses ............................................................................... 9-16
SDRAM Write Accesses .............................................................................. 9-18
SDRAM Refresh Timing.............................................................................. 9-20
Chapter 10
DMA Controller
10.1
10.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
DMA Data Transfer Types ............................................................................... 10-1
DMA Address Modes....................................................................................... 10-2
DMA Controller Registers................................................................................ 10-2
DMA Mode Register (DMR)........................................................................ 10-2
DMA Interrupt Register (DIR)..................................................................... 10-4
DMA Source Address Register (DSAR)...................................................... 10-5
DMA Destination Address Register (DDAR).............................................. 10-6
DMA Byte Count Register (DBCR)............................................................. 10-6
Chapter 11
Ethernet Module
11.1
11.1.1
11.2
11.3
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.4.7
11.4.8
Overview........................................................................................................... 11-1
Features......................................................................................................... 11-1
Module Operation............................................................................................. 11-2
Transceiver Connection.................................................................................... 11-3
FEC Frame Transmission ................................................................................. 11-4
FEC Frame Reception................................................................................... 11-5
CAM Interface.............................................................................................. 11-7
Ethernet Address Recognition...................................................................... 11-7
Hash Table Algorithm .................................................................................. 11-8
Interpacket Gap Time ................................................................................... 11-9
Collision Handling........................................................................................ 11-9
Internal and External Loopback.................................................................... 11-9
Ethernet Error-Handling Procedure.............................................................. 11-9