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參數資料
| 型號： | MCF5407 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ColdFire Integrated Microprocessor(ColdFire微處理器) |
| 中文描述： | 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 7/24頁 |
| 文件大?。?/td> | 296K |
| 代理商： | MCF5407 |
MCF5407 Integrated ColdFire¨ Microprocessor
7
ColdFire Module Description
1.3.1.2 Operand Execution Pipeline (OEP)
The prefetched instruction stream is gated from the FIFO buffer into the Tve-stage OEP. The OEP consists
of two, traditional two-stage RISC compute engines with a register Tle access feeding an arithmetic/logic
unit (ALU). The compute engine located at the top of the OEP is typically used for operand memory address
calculations (the address ALU), while the compute engine located at the bottom of the pipeline is used for
instruction execution (the execution ALU). The resulting structure provides 3.9 Gbytes/S data operand
bandwidth at 162 MHz to the two compute engines and supports single-cycle execution speeds for most
instructions, including all load, store and most embedded-load operations. In response to users and
developers, the V4 design supports execution of the ColdFire Revision B instruction set, which adds a small
number of new instructions to improve performance and code density.
The OEP also implements two advanced performance features. It dynamically determines the appropriate
location of instruction execution (either in the address ALU or the execution ALU) based on the pipeline
state. The address compute engine, in conjunction with register renaming resources, can be used to execute
a number of heavily-used opcodes and forward the results to subsequent instructions without any pipeline
stalls. Additionally, the OEP implements instruction folding techniques involving MOVE instructions so
that two instructions can be issued in a single machine cycle. The resulting microarchitecture approaches
the performance of a full superscalar implementation, but at a much lower silicon cost.
1.3.1.3 MAC Module
The MAC unit provides signal processing capabilities for the MCF5407 in a variety of applications
including digital audio and servo control. Integrated as an execution unit in the processor's OEP, the MAC
unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input
operands are supported by this design in addition to a full set of extensions for signed and unsigned integers
plus signed, Txed-point fractional input operands.
1.3.1.4 Integer Divide Module
Some embedded applications can beneTt greatly from the integer divide unit. Integrated as another engine
in the processors OEP, the divide module performs a variety of operations using signed and unsigned
integers. The module supports word and longword divides producing quotients and/or remainders.
1.3.2 Harvard Architecture
A Harvard memory architecture is implemented to support the increased bandwidth requirements of the V4
processor pipelines. In this design featuring separate instruction and data buses to the processor-local
memories, available bandwidth to the processor reaches 1.3 Gbytes/S at 162 MHz and conicts between
instruction fetches and operand accesses are removed.
1.3.2.1 16-Kbyte Instruction Cache/8-Kbyte Data Cache
Attached to the Harvard memory architecture are a 16-Kbyte instruction cache and an 8-Kbyte data cache.
These four-way, set-associative designs improve system performance by providing pipelined, single-cycle
access on instruction fetches and operand accesses that hit in these memories.
As with all ColdFire caches, these controllers implement a non-lockup, streaming design to maximize
performance. The use of processor-local memories decouples performance from external memory speeds
and increases available bandwidth for external devices or the on-chip 4-channel DMA.
Both caches implement line-Tll buffers to optimize the performance of line-sized (16-byte) burst accesses.
Additionally, the data cache supports operation of copyback, write-through or noncacheable modes. A 4-
entry, 32-bit buffer is used for cache line push operations and can be conTgured for deferred write buffering
while in write-through or non-cacheable modes.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MCF5407AI162 | 功能描述:微處理器 - MPU MCF5407 V4CORE 4KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5407AI220 | 功能描述:微處理器 - MPU MCF5407 V4CORE 4KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5407CAI162 | 功能描述:微處理器 - MPU MCF5407 V4CORE 4KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5407CAI220 | 功能描述:微處理器 - MPU MCF5407 V4CORE 4KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5407CFT162 | 功能描述:IC MPU 32B 162MHZ COLDF 208-FQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MCF540x 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設備:POR，PWM，溫度傳感器，WDT 輸入/輸出數:21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數據轉換器:A/D 6x12b 振蕩器型:內部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
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