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參數資料
| 型號： | MCM101524B15 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M x 4 Bit Fast Static Random Access Memory with ECL I/O |
| 中文描述： | 100萬× 4位靜態隨機存取快速與ECL的I /內存? |
| 文件頁數： | 2/8頁 |
| 文件大?。?/td> | 454K |
| 代理商： | MCM101524B15 |
MCM101524
2
MOTOROLA FAST SRAM
TRUTH TABLE
(X = Don’t Care)
S
W
Operation
Data
Output
Current
H
X
Not Enabled
X
L
—
L
H
Read
X
Q
IEE
IEE
L
L
Write
X
L
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Symbol
Value
Unit
VEE Pin Potential (to Ground)
Voltage Relative to VCC for Any Pin
Except VEE
VEE
Vin, Vout
– 7.0 to + 0.5
V
VEE – 0.5 to+ 0.5
V
Output Current (per I/O)
Iout
PD
Tbias
TJ
Tstg
– 50
mA
Power Dissipation
2.0
W
Temperature Under Bias
– 30 to + 85
°
C
Operating Temperature
0 to + 60
°
C
Storage Temperature — Plastic
– 55 to + 125
°
C
NOTE:Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the OPERATING CONDI-
TIONS. Exposure to higher than recommended voltages for extended periods of time
could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 0 V, VEE = – 5.2 V
±
5%, TJ = 0 to + 60
°
C, Unless Otherwise Noted)
DC OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VEE
VIH
VIL
VOH
VOL
IIL
IIH
IIL(CS)
IEE
IEEQ
VOH/
VEE
VOL/
VEE
– 5.46
– 5.2
– 4.94
V
Input High Voltage
– 1165
—
– 880
mV
Input Low Voltage
– 1810
—
– 1475
mV
Output High Voltage
– 1025
—
– 880
mV
Output Low Voltage
– 1810
—
– 1620
mV
Input Low Current
– 50
—
—
μ
A
Input High Current
—
—
220
μ
A
Chip Select Input Low Current
Operating Power Supply Current: tAVAV = 20 ns (All Outputs Open)*
0.5
—
170
μ
A
—
—
– 195
mA
Quiescent Power Supply Current: fo = 0 MHz (Outputs Open)
Voltage Compensation (VOH)
Voltage Compensation (VOL)
* Address Increment
—
—
– 150
mA
±
35 mV/V @ – 4.94 to – 5.46 V
±
60 mV/V @ – 4.94 to – 5.46 V
RISE/FALL TIME CHARACTERISTICS
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Rise Time
tr
tf
20% to 80%
0.5
1.0
1.5
ns
Output Fall Time
20% to 80%
0.5
1.0
1.5
ns
CAPACITANCE
(f = 1.0 MHz, TA = 25
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
Address and Data
S, W
Cin
Cck
3.5
4
7
7
pF
Output Capacitance
Q
Cout
4
8
pF
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is ad-
vised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to these high
impedance circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifica-
tions shown in the tables, after thermal equi-
librium has been established. The circuit is
in a test socket or mounted on a printed cir-
cuit board and transverse air flow of at least
500 linear feet per minute is maintained.
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