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參數資料
| 型號： | MCM101524B15 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M x 4 Bit Fast Static Random Access Memory with ECL I/O |
| 中文描述： | 100萬× 4位靜態隨機存取快速與ECL的I /內存? |
| 文件頁數： | 3/8頁 |
| 文件大小： | 454K |
| 代理商： | MCM101524B15 |
MCM101524
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VEE = – 5.2 V
±
5%, VCC = 0 V, TJ = 0 to +60
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
– 1.7 V to – 0.9 V (See Figure 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . .
1 ns
50%
Output Timing Measurement Reference Level
VOH = – 1165 mV
VOL = – 1475 mV
See Figure 2
. .
Output Load (AC Test Circuit)
. . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING
(See Notes 1 and 2)
MCM101524–12
MCM101524–15
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tSLQV
tSHQL
tAXQX
tSLIEEH
tSHIEEL
12
—
15
—
ns
2, 3
Address Access Time
—
12
—
15
ns
Chip Select Access Time
—
12
—
15
ns
6
Select High to Output Low
0
8
0
9
ns
Output Hold from Address Change
4
—
4
—
ns
Power Up Time
0
—
0
—
ns
4
Power Down Time
—
12
—
15
ns
4
NOTES:
1. W is high for read cycle.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. This parameter is sampled and not 100% tested.
5. Device is continuously selected (S
≤
VIL).
6. Addresses valid prior to or coincident with S going low.
80%
50%
20%
Figure 1. Input Levels
Figure 2. AC Test Circuit
AC TEST CONDITIONS
20%
50%
80%
– 0.9 V
– 1.7 V
tf
tr
VCC
VEE
Q
CL
RL
– 2.0 V
0.01
μ
F
0.1
μ
F
tr = Rise Time
tf = Fall Time
50% = Timing Reference Levels
RL = 50
CL = 30 pF
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