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參數資料
| 型號： | MCM6323ATS10 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 10 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 181K |
| 代理商： | MCM6323ATS10 |
MCM6323A
1
MOTOROLA FAST SRAM
Motorola, Inc. 1997
Product Preview
64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6323A is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention
problems. Separate byte enable controls (LB and UB) allow individual bytes to be
written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits.
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack-
age and a 44–lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.
Single 3.3 V
±
0.3 V Power Supply
Fast Access Time: 10, 12, 15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 140/135/130 mA Maximum, Active AC
Industrial Temperature Option: – 40 to + 85
°
C
Part Number: SCM6323AYJ10A
BLOCK DIAGRAM
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFERS
WRITE
ENABLE
BUFFER
BYTE
ENABLE
BUFFER
ROW
DECODER
COLUMN
DECODER
64K x 16
BIT
MEMORY
ARRAY
HIGH
BYTE
OUTPUT
BUFFER
8
HIGH
BYTE
WRITE
DRIVER
LOW
BYTE
OUTPUT
BUFFER
LOW
BYTE
WRITE
DRIVER
SENSE
AMPS
G
W
LB
8
8
8
8
8
8
8
9
A
CHIP
ENABLE
BUFFER
E
UB
7
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
16
16
8
DQb
8
DQa
This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.
Order this document
by MCM6323A/D
SEMICONDUCTOR TECHNICAL DATA
MCM6323A
YJ PACKAGE
400 MIL SOJ
CASE 919–01
PIN ASSIGNMENT
A
E
W
G
UB
LB
DQa
DQb
VDD
VSS
NC
Address Input
Chip Enable
Write Enable
Output Enable
Upper Byte
Lower Byte
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Lower Data Input/Output
Upper Data Input/Output
+ 3.3 V Power Supply
Ground
No Connection
PIN NAMES
5
6
4
3
2
1
10
11
12
13
14
15
16
17
18
19
20
21
22
9
8
7
36
35
34
33
37
38
39
40
41
42
43
44
E
A
A
A
A
A
DQa
DQa
DQa
VDD
VSS
DQa
UB
LB
G
A
A
A
DQb
VSS
VDD
DQb
DQb
DQb
25
24
23
26
27
28
29
30
31
32
DQb
NC
DQb
DQb
DQb
A
NC
A
A
A
W
A
DQa
DQa
DQa
DQa
A
A
NC
A
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–01
REV 1
10/17/97
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MCM6323ATS10R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| MCM6323ATS12 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| MCM6323ATS12R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| MCM6323ATS15 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| MCM6323ATS15R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
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