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參數資料
| 型號： | MCM6323AYJ15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁數： | 4/12頁 |
| 文件大小： | 181K |
| 代理商： | MCM6323AYJ15 |
MCM6323A
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
0.3 V, TA = 0 to +70
°
C, Unless Otherwise Noted)
(TA = – 40 to + 85
°
C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level
Logic Input Pulse Levels
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.50 V
0 to 3.0 V
. . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.50 V
. . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1
READ CYCLE TIMING
(See Notes 1, 2, 3, and 4)
Parameter
Symbol
b l
MCM6323A–10
MCM6323A–12
MCM6323A–15
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
tBLQV
tBLQX
tBHQZ
10
—
12
—
15
—
ns
5
Address Access Time
—
10
—
12
—
15
ns
Enable Access Time
—
10
—
12
—
15
ns
Output Enable Access Time
—
4
—
5
—
6
ns
6
Output Hold from Address Change
3
—
3
—
3
—
ns
Enable Low to Output Active
3
—
3
—
3
—
ns
6, 7, 8
Output Enable Low to Output Active
0
—
0
—
0
—
ns
6, 7, 8
Enable High to Output High–Z
—
4
—
5
—
6
ns
6, 7, 8
Output Enable High to Output High–Z
—
4
—
5
—
6
ns
6, 7, 8
Byte Enable Access Time
—
4
—
5
—
6
ns
Byte Enable Low to Output Active
0
—
0
—
0
—
ns
6, 7, 8
Byte High to Output High–Z
0
5
0
5
0
5
ns
6, 7, 8
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization, or elimination of bus contention conditions is necessary during read and write cycles.
3. Device is continuously selected (E = VIL, G = VIL, and LB and/or UB = VIL).
4. Addresses valid prior to or coincident with E going low.
5. All read cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured 200 mV from steady–state voltage.
7. At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from
device to device.
8. This parameter is sampled and not 100% tested.
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相關代理商/技術參數 |
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