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參數資料
| 型號： | MCM63P631ATQ117R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K X 32 CACHE SRAM, 4.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 4/16頁 |
| 文件大?。?/td> | 228K |
| 代理商： | MCM63P631ATQ117R |
MCM63P631A
4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADSC
Input
Synchronous Address Status Controller: Active low, is used to latch a
new external address. Used to initiate a READ, WRITE or chip
deselect.
84
ADSP
Input
Synchronous Address Status Processor: Initiates READ or chip
deselect cycle (exception — chip deselect does not occur when ADSP
is asserted and SE1 is high).
83
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29
DQx
I/O
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
86
G
Input
Asynchronous Output Enable.
89
K
Input
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
64
ZZ
Input
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4, 11, 15, 20, 27, 41,
54, 61, 65, 70, 77, 91
VDD
Supply
Power Supply: 3.3 V + 10%, – 5%.
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
VSS
Supply
Ground.
1, 14, 16, 30, 38, 39,
42, 43, 50, 51, 66, 80
NC
—
No Connection: There is no connection to the chip.
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| MCM63P631ATQ66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
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| MCM63P631TQ117 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
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