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參數資料
型號: MCM63P631ATQ75
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: ER 4C 4#12 SKT RECP BOX
中文描述: 64K X 32 CACHE SRAM, 7 ns, PQFP100
封裝: TQFP-100
文件頁數: 8/16頁
文件大小: 228K
代理商: MCM63P631ATQ75
MCM63P631A
8
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD
VIL
VIH
3.135
3.3
3.6
V
Input Low Voltage
– 0.5
0.8
V
Input High Voltage
2.0
VDD + 0.5
V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V
Vin
VDD)
Output Leakage Current (0 V
Vin
VDD)
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max, VDD = Max)
Ilkg(I)
Ilkg(O)
IDDA
±
1
μ
A
1, 2
±
1
μ
A
MCM63P631A–117
MCM63P631A–100
MCM63P631A–75
MCM63P631A–66
TBD
mA
3, 4, 5
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static
at CMOS Levels)
ISB2
TBD
mA
6, 7
Sleep Mode Supply Current (Sleep Mode, Freq = Max, VDD = Max,
All Other Inputs Static at CMOS Levels, ZZ
VDD – 0.2 V)
IZZ
2
mA
2, 7, 8
TTL Standby (Device Deselected, Freq = 0, VDD = Max,
All Inputs Static at TTL Levels)
ISB3
TBD
mA
6, 9
Clock Running (Device Deselected, Freq = Max,
VDD = Max, All Inputs Toggling at CMOS Levels)
MCM63P631A–117
MCM63P631A–100
MCM63P631A–75
MCM63P631A–66
ISB4
TBD
mA
6, 7
Static Clock Running (Device Deselected, Freq = Max,
VDD = Max, All Inputs Static at TTL Levels)
MCM63P631A–117
MCM63P631A–100
MCM63P631A–75
MCM63P631A–66
ISB5
TBD
mA
6, 9
Output Low Voltage (IOL = 8 mA)
Output High Voltage (IOH = – 4 mA)
NOTES:
1. LBO pin has an internal pullup and will exhibit leakage currents of
±
5
μ
A.
2. ZZ pin has an internal pulldown and will exhibit leakage currents of
±
5
μ
A.
3. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V).
4. All addresses transition simultaneously low (LSB) and then high (MSB).
5. Data states are all zero.
6. Device in Deselected mode as defined by the Truth Table.
7. CMOS levels are Vin
VSS + 0.2 V or
VDD – 0.2 V.
8. Device in Sleep Mode as defined by the Asynchronous Truth Table.
9. TTL levels are Vin
VIL or
VIH.
VOL
VOH
0.4
V
2.4
V
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
CI/O
3
5
pF
Input/Output Capacitance
6
8
pF
相關PDF資料
PDF描述
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參數描述
MCM63P631ATQ75R 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P631TQ117 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P631TQ117R 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P631TQ4.5 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P631TQ4.5R 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
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