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參數資料
| 型號： | MCM63P818TQ66R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 256K X 18 CACHE SRAM, 7 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 11/27頁 |
| 文件大小： | 328K |
| 代理商： | MCM63P818TQ66R |
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MCM63P636
11
MOTOROLA FAST SRAM
READ/WRITE CYCLE TIMING
(See Notes 1 and 2)
Parameter
Symbol
b l
MCM63P636–250
MCM63P636–225
MCM63P636–200
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Clock Cycle Time
tKHKH
tKH
tKL
tSKHSKH
tSKH
tSKL
tKHSKH
tKHQV
tKHQX
tKHQZ
tSKHSTV
tAVKH
tSVKH
tEVKH
tDVKH
tQVSTV
tWVKH
4
—
4.4
—
5
—
ns
3, 4
Clock High Time
1.06
—
1.24
—
1.46
—
ns
4
Clock Low Time
1.06
—
1.24
—
1.46
—
ns
4
Strobe Clock Cycle Time
4
—
4.4
—
5
—
ns
3, 4
Strobe Clock High Time
1.06
—
1.24
—
1.46
—
ns
4
Strobe Clock Low Time
1.06
—
1.24
—
1.46
—
ns
4
Rising K to Rising SK
1.6
2.4
1.8
2.6
2.1
2.9
3
Clock Access Time
—
3.9
—
4.3
—
4.9
ns
3
Clock to Output Low–Z
0
—
0
—
0
—
ns
5, 6
Clock to Output High–Z
—
3.9
—
4.3
—
4.9
ns
5, 6
Strobe Clock Access Time
—
3.9
—
4.3
—
4.9
ns
3
Setup Times:
Address
ADS
Chip Enable
Data In
Data Out
Write
0.5
1.2
0.5
1.2
1
1.2
—
0.5
1.5
0.5
1.5
1.1
1.5
—
0.5
1.5
0.5
1.5
1.15
1.5
—
ns
3
Hold Times:
Address
ADS
Chip Enable
Data In
Data Out
Write
tKHAX
tKHSX
tKHEX
tKHDX
tSTVQX
tKHWX
4
0.5
4
0.5
1
0.5
—
4.4
0.5
4.4
0.5
1.1
0.5
—
5
0.5
5
0.5
1.15
0.5
—
ns
3
NOTES:
1. Reads and writes are as defined in the Truth Table.
2. All read and write cycle timings are referenced from K, SK, or data strobes.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. Refer to Figure 5 for input reference levels.
5. This parameter is sampled and not 100% tested.
6. Measured at
±
200 mV from steady state.
VIH
VIL
VDDQ
VSS
VDDQ/2
tKH, tSKH
tKL, tSKL
tKHKH, tSKHSKH
Figure 6. AC Timing Diagram Clock Reference
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