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參數(shù)資料
| 型號(hào)： | MCM63P818TQ66R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 256K X 18 CACHE SRAM, 7 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大小： | 328K |
| 代理商： | MCM63P818TQ66R |
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MCM63P636
19
MOTOROLA FAST SRAM
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the RAMs critical speed path. Nevertheless,
the RAM supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the
TAPs operation) and can be expected to function in a manner
that does not conflict with the operation of devices with IEEE
Standard 1149.1 compliant TAPs. The TAP operates using a
2.5 V tolerant logic level signaling.
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfering with normal
operation of the device, TRST should be tied low and TCK,
TDI, and TMS should be pulled through a resistor to 2.0 V.
TDO should be left unconnected.
TAP DC OPERATING CHARACTERISTICS
(TA = 0 to 70
°
C, Unless Otherwise Noted)
Parameter
Symbol
Min
Max
Unit
Notes
Input Logic Low
VIL1
– 0.5
0.35 x VDDQ
V
Input Logic High
VIH1
0.65 x VDDQ
2.5
V
Input Leakage Current
Ilkg
—
±
10
μ
A
1
Output Logic Low
VOL1
VSS – 0.5
0.4
V
2
Output Logic High
VOH1
VDDQ – 0.4
VDDQ + 0.5
V
NOTES:
1. 0 V
≤
Vin
≤
VDDQ for all logic input pins.
2. For VOL = 0.4 V, 14 mA
≤
IOL
≤
28 mA.
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