- 您現在的位置：買賣IC網 > PDF目錄371088 > MCM63R918A (Motorola, Inc.) 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) PDF資料下載
參數資料
| 型號： | MCM63R918A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| 中文描述： | 8MBit快速同步后寫入靜態存儲器（800萬位同步遲寫快速靜態內存） |
| 文件頁數： | 13/21頁 |
| 文件大?。?/td> | 427K |
| 代理商： | MCM63R918A |
MCM63R836A
MCM63R918A
13
MOTOROLA FAST SRAM
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals are registered on the rising edge of the
CK clock. These signals must meet the setup and hold times
shown in the AC Characteristics table. On the rising edge of
the following clock, read data is clocked into the output regis-
ter and available at the outputs at tKHQV. During this same
cycle a new read address can be applied to the address pins.
A deselect cycle (dead cycle) must occur prior to a write
cycle. Read cycles may follow write cycles immediately.
SS and SW control output drive. Chip deselect via a high
on SS at the rising edge of the CK clock has its effect on the
output drivers after the next rising edge of the CK clock. SW
low deselects the output drivers immediately (on the same
cycle).
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing
parameters described for synchronous write input (SW)
apply to each of the byte write enable inputs (SBa, SBb,
etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable
inputs in conjunction with the synchronous write input (SW).
It is important to note that writing any one byte will inhibit a
read of all bytes at the current address. The RAM cannot si-
multaneously read one byte and write another at the same
address. A write cycle initiated with none of the byte write
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent
operation. This occurs in all cases, whether there is a byte
write or a full word is written.
PROGRAMMABLE IMPEDANCE OPERATION
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to VSS through a precision
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, 250
resistor will give an output
impedance of 50
.
Impedance updates occur during write and deselect
cycles.
The actual change in the impedance occurs in small incre-
ments and is binary. The binary impedance has 256 values
and therefore, there are no significant disturbances that
occur on the output because of this smooth update method.
At power up, the output impedance will take up to 65,000
cycles for the impedance to be completely updated. At
recovery from sleep mode, the previously programmed value
will be recovered.
POWER UP AND INITIALIZATION
The following supply voltage application sequence is
recommended: VSS, VDD, then VDDQ. Please note, per the
Absolute Maximum Ratings table, VDDQ is not to exceed
VDDQ + 0.5 V or 2.0 V max, whatever the instantaneous
value of VDD. Once supplies have reached specification
levels, a minimum dwell of 1.0 ms with CK clock inputs
cycling is required before beginning normal operations. At
power up the output impedance will be set at approximately
50
as stated above.
相關PDF資料 |
PDF描述 |
|---|---|
| MCM63R836A | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| MCM63Z736 | 128K x 36 Bit Synchronous Fast Static RAM(128K x 36位同步快速靜態RAM) |
| MCM63Z818 | 256Kx18 Bit Synchronous Fast Static RAM(256Kx18位同步快速靜態RAM) |
| MCM64AF32 | 256K Asynchronous Secondary Cache Module for Pentium |
| MCM64AF32SG15 | 256K Asynchronous Secondary Cache Module for Pentium |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MCM63R918FC3.0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.0R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.3R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
發布緊急采購，3分鐘左右您將得到回復。