- 您現在的位置：買賣IC網 > PDF目錄371088 > MCM63R918A (Motorola, Inc.) 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) PDF資料下載
參數資料
| 型號： | MCM63R918A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| 中文描述： | 8MBit快速同步后寫入靜態存儲器（800萬位同步遲寫快速靜態內存） |
| 文件頁數： | 18/21頁 |
| 文件大小： | 427K |
| 代理商： | MCM63R918A |
MCM63R836A
MCM63R918A
18
MOTOROLA FAST SRAM
TAP CONTROLLER INSTRUCTION SET
OVERVIEW
There are two classes of instructions defined in the IEEE
Standard 1149.1–1990; the standard (public) instructions
and device specific (private) instructions. Some public
instructions, are mandatory for IEEE 1149.1 compliance.
Optional public instructions must be implemented in pre-
scribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully imple-
mented. The TAP on this device may be used to monitor all
input and I/O pads, but can not be used to load address,
data, or control signals into the RAM or to preload the I/O
buffers. In other words, the device will not perform IEEE
1149.1 EXTEST, INTEST, or the preload portion of the
SAMPLE/PRELOAD command.
When the TAP controller is placed in capture–IR state, the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state
the instruction register is placed between TDI and TDO. In
this state, the desired instruction is serially loaded through
the TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS
The BYPASS instruction is loaded in the instruction regis-
ter when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the instruction register, moving the TAP controller
into the capture–DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK), it is
possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e., in a metast-
able state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results can not be
expected. RAM input signals must be stabilized for long
enough to meet the TAPs input data capture setup plus hold
time (tCS plus tCH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not
implemented in this device, moving the controller to the
update–DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not IEEE 1149.1
compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device. Therefore, this
device is not IEEE 1149.1 compliant. Nevertheless, this
RAMs TAP does respond to an all 0s instruction, as follows.
With the EXTEST (000) instruction loaded in the instruction
register, the RAM responds just as it does in response to the
SAMPLE/PRELOAD instruction described above, except the
DQ pins are forced to High–Z any time the instruction is
loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at power up and any time the controller
is placed in the test–logic–reset state.
THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE–Z
If the SAMPLE–Z instruction is loaded in the instruction
register, all DQ pins are forced to an inactive drive state
(High–Z) and the boundary scan register is connected
between TDI and TDO when the TAP controller is moved to
the shift–DR state.
THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP
Do not use these instructions; they are reserved for future
use.
相關PDF資料 |
PDF描述 |
|---|---|
| MCM63R836A | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| MCM63Z736 | 128K x 36 Bit Synchronous Fast Static RAM(128K x 36位同步快速靜態RAM) |
| MCM63Z818 | 256Kx18 Bit Synchronous Fast Static RAM(256Kx18位同步快速靜態RAM) |
| MCM64AF32 | 256K Asynchronous Secondary Cache Module for Pentium |
| MCM64AF32SG15 | 256K Asynchronous Secondary Cache Module for Pentium |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MCM63R918FC3.0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.0R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.3R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R918FC3.7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
發布緊急采購，3分鐘左右您將得到回復。