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參數資料
| 型號： | MCM64AF32SG15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256K Asynchronous Secondary Cache Module for Pentium |
| 中文描述： | 32K X 64 CACHE TAG SRAM MODULE, 22 ns, DMA160 |
| 文件頁數： | 9/12頁 |
| 文件大小： | 190K |
| 代理商： | MCM64AF32SG15 |
MCM64AF32
9
MOTOROLA FAST SRAM
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
Figure 1A Unless Otherwise Noted
TAG RAM READ CYCLE
(See Notes 1 and 5)
– 15
Parameter
Symbol
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tAXQX
15
—
ns
2
Address Access Time
—
15
ns
Output Hold from Address Change
4
—
ns
3, 4
NOTES:
1. CWE is high for read cycle.
2. All timings are referenced from the last valid address to the first address transition.
3. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
4. This parameter is sampled and not 100% tested.
5. Device is continuously selected (COE = VIL).
TAG RAM READ CYCLE
(See Note 5)
Q (DATA OUT)
A5 – A17
DATA VALID
PREVIOUS DATA VALID
tAVAV
tAXQX
tAVQV
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