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參數資料
| 型號： | MCM64E836 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8M Bit synchronous late write fast static RAM(8M位同步遲寫快速靜態RAM) |
| 中文描述： | 晚8分位同步靜態隨機存儲器寫入速度（800萬位同步遲寫快速靜態內存） |
| 文件頁數： | 17/24頁 |
| 文件大小： | 503K |
| 代理商： | MCM64E836 |
MCM64E918
MCM64E836
17
MOTOROLA FAST SRAM
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
Output Timing Reference Level
0 to 2.2 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
1 V/ns (20% to 80%)
. . . . . . . . . . . . . . .
1.1 V
1.1 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Test Load
50
Parallel Terminated T–Line with 20 pF
Receiver Input Capacitance
. . . . . . . . . . . . . . .
. . . . .
Test Load Termination Supply Voltage (VT)
1.1 V
TAP CONTROLLER TIMING
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tTHTH
100
—
ns
Clock High Time
tTHTL
tTLTH
tMVTH
tTHMX
tDVTH
tTHDX
tCS
tCH
tTLQX
tTLOV
40
—
ns
Clock Low Time
40
—
ns
TMS Setup
10
—
ns
TMS Hold
10
—
ns
TDI Valid to TCK High
10
—
ns
TCK High to TDI Don’t Care
10
—
ns
Capture Setup
10
—
ns
1
Capture Hold
10
—
ns
1
TCK Low to TDO Unknown
0
—
ns
TCK Low to TDO Valid
—
20
ns
NOTE:
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.
AC TEST LOAD
DEVICE
UNDER
TEST
50
50
1.1 V
20 pF
tTHDX
tTLQV
tTLQX
tDVTH
tTLTH
tTHMX
tMVTH
TAP CONTROLLER TIMING DIAGRAM
tTHTH
TEST CLOCK
(TCK)
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
TEST DATA OUT
(TDO)
tTHTL
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