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參數(shù)資料
| 型號： | MCM64PC64TSG66 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
| 中文描述： | 64K X 64 CACHE TAG SRAM MODULE, 8 ns, DMA160 |
| 封裝： | CARD EDGE MODULE-160 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 167K |
| 代理商： | MCM64PC64TSG66 |
MCM64PC32T
MCM64PC64T
12
MOTOROLA FAST SRAM
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
0.3 V, TJ = 20 to + 110
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
Figure 3 Unless Otherwise Noted
TAG RAM READ CYCLE
(See Notes 1 and 2)
– 15
Parameter
Symbol
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tAXQX
15
—
ns
3
Address Access Time
—
15
ns
Output Hold from Address Change
4
—
ns
4, 5
NOTES:
1. CWE is high for read cycle.
2. Device is continuously selected (CG = VIL).
3. All timings are referenced from the last valid address to the first address transition.
4. Transition is measured
±
500 mV from steady–state voltage with load of Figure 3b.
5. This parameter is sampled and not 100% tested.
TAG RAM READ CYCLE
(See Note 5)
Q (DATA OUT)
Ax (ADDRESS)
DATA VALID
PREVIOUS DATA VALID
tAVAV
tAXQX
tAVQV
OUTPUT
Z0 = 50
50
VL = 1.5 V
(a)
(b)
5 pF
3.3 V
OUTPUT
351
317
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
Figure 3. Test Loads
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