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參數資料
型號: MCM64PC64TSG66
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium
中文描述: 64K X 64 CACHE TAG SRAM MODULE, 8 ns, DMA160
封裝: CARD EDGE MODULE-160
文件頁數: 9/16頁
文件大小: 167K
代理商: MCM64PC64TSG66
MCM64PC32T
MCM64PC64T
9
MOTOROLA FAST SRAM
DATA RAMs READ/WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
MCM64PC32T–66
MCM64PC32T–66
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tKHKL
tKLKH
tAVKH
tADSVKH
tDVKH
tWVKH
tADVVKH
tEVKH
15
ns
Clock Access Time
8
ns
5
Output Enable to Output Valid
6
ns
5
Clock High to Output Active
0
ns
5, 7
Clock High to Output Change
2
ns
5, 7
Output Enable to Output Active
0
ns
5, 7
Output Disable to Q High–Z
8
ns
6, 7
Clock High to Q High–Z
2
8
ns
6, 7
Clock High Pulse Width
5
ns
Clock Low Pulse Width
5
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
2.5
ns
4
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHADVX
tKHEX
0.5
ns
4
NOTES:
1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high.
2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. Tested per AC Test Load.
6. Measured at
±
200 mV from steady state. Tested per High–Z Test Load.
7. This parameter is sampled and is not 100% tested.
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