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參數資料
型號: MCM64PD64SG66
廠商: MOTOROLA INC
元件分類: SRAM
英文描述: 8 BIT MCU - LJ12 SERIES
中文描述: 64K X 64 CACHE SRAM MODULE, 8 ns, DMA160
封裝: CARD EDGE MODULE-160
文件頁數: 4/12頁
文件大小: 190K
代理商: MCM64PD64SG66
MCM64AF32
4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations
Symbol
Type
Description
21, 22, 23, 24, 28, 29,
102, 103, 104, 106, 108, 109, 110
A5 – A17
Input
Address Inputs: These inputs are latched into data RAMs and must
meet setup and hold times. The tag RAM addresses are not latched.
(See Block Diagram).
9, 89
CAA3,
CAA4
Input
Cache Address A: Low order address inputs for bursting. Not latched.
16, 97
CAB3,
CAB4
Input
Cache Address B: Low order address inputs for bursting. Not latched.
98
CALE
Input
Address Latch Enable: Active low signal latches A5 – A17.
11, 12, 13, 14, 92, 93, 94, 96
CWE0 –
CWE7
Input
Cache Data Write Enable: Active low write signal for data RAMs.
8
TWE
Input
Tag Write Enable: Active low write signal for tag RAMs.
CS
Input
Chip Select: Active low chip enable for tag and data RAMs. Not used.
91
COE
Input
Cache Output Enable: Asynchronous active low output enable for data
RAMs.
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
DQ0 –
DQ63
I/O
Data I/O
2, 3, 4, 5, 82, 83, 84, 85
TIO0 –
TIO7
I/O
Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
33, 34, 112, 113, 114
PD0 –
PD4
Presence Detect: See Presence Detect Table.
7, 15, 25, 39, 52, 60, 68, 76
VCC3
VCC5
VSS
Supply
Power Supply: 3.3 V
±
5%.
87, 95, 105, 119, 132, 140, 148, 156
Supply
Power Supply: 5.0 V
±
5%.
1, 10, 19, 27, 35, 37, 43, 48, 56, 64,
72, 80, 81, 90, 99, 107, 115, 117,
123, 128, 136, 144, 152, 160
Supply
Ground
6, 17, 18, 20, 26, 30, 31, 32, 36,
86, 88, 100, 101, 111, 116
NC
No Connection: There is no connection to the module.
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