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參數(shù)資料
| 型號(hào)： | MCM6709AJ8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 4 Bit Static RAM |
| 中文描述： | 64K X 4 STANDARD SRAM, 8 ns, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-28 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 147K |
| 代理商： | MCM6709AJ8 |
MCM6709A
2–6
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled, See Notes 1 and 2)
MCM6709A–8
MCM6709A–10
MCM6709A–12
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVEL
tAVEH
tELEH,
tELWH
8
—
10
—
12
—
ns
3
Address Setup Time
0
—
0
—
0
—
ns
Address Valid to End of Write
8
—
9
—
10
—
ns
Chip Enable to End of Write
7
—
8
—
9
—
ns
4, 5
Data Valid to End of Write
tDVEH
tEHDX
tEHAX
4
—
5
—
6
—
ns
Data Hold Time
0
—
0
—
0
—
ns
Write Recovery Time
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
DATA VALID
HIGH–Z
tAVAV
tAVEH
tAVEL
tELWH
tEHAX
tDVEH
tEHDX
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tELEH
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