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參數資料
型號: MCM67M618AFN9
廠商: MOTOROLA INC
元件分類: SRAM
英文描述: 64K x 18 Bit BurstRAM Synchronous Fast Static RAM
中文描述: 64K X 18 CACHE SRAM, 9 ns, PQCC52
封裝: PLASTIC, LCC-52
文件頁數: 3/12頁
文件大小: 206K
代理商: MCM67M618AFN9
MCM67M618A
3
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE
(See Notes 1, 2, and 3)
E
TSP
TSC
BAA
LW or UW
K
Address
Operation
H
L
X
X
X
L–H
N/A
Deselected
H
X
L
X
X
L–H
N/A
Deselected
L
L
X
X
X
L–H
External Address
Read Cycle, Begin Burst
L
H
L
X
L
L–H
External Address
Write Cycle, Begin Burst
L
H
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
Operation
G
I/O Status
Read
L
Data Out
Read
H
High–Z
Write
X
High–Z — Data In
Deselected
X
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
Vin, Vout
– 0.5 to + 7.0
V
Voltage Relative to VSS for Any
Pin Except VCC
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
PD
Tbias
TA
Tstg
±
30
mA
Power Dissipation
1.6
W
Temperature Under Bias
– 10 to + 85
°
C
Operating Temperature
0 to +70
°
C
Storage Temperature
– 55 to + 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
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