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參數(shù)資料
型號: MCM67Q709A
廠商: Motorola, Inc.
英文描述: 128Kx9 Bit Synchronous Fast Static RAM(128Kx9 Bit同步快速靜態(tài)存儲器)
中文描述: 128Kx9位同步快速靜態(tài)存儲器(128Kx9位同步快速靜態(tài)存儲器)
文件頁數(shù): 1/12頁
文件大小: 145K
代理商: MCM67Q709A
MCM67Q709A
1
MOTOROLA FAST SRAM
Motorola, Inc. 1999
128K x 9 Bit Separate I/O
Synchronous Fast Static RAM
The MCM67Q709A is a 1,179,648–bit static random access memory,
organized as 131,072 words of 9 bits. It features separate TTL input and output
buffers, which drive 3.3 V output levels and incorporates input and output regis-
ters on–board with high speed SRAM. It also features transparent–write and data
pass–through capabilities.
The synchronous design allows for precise cycle control with the use of an
external single clock (K). The addresses (A0 – A16), data input (D0 – D8), data
output (Q0 – Q8), write enable (W), chip enable (E), and output enable (G), are
registered in on the rising edge of clock (K).
The control pins (E, W, G) function differently in comparison to most synchro-
nous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
The pass–through function is always enabled. E high disables the write to the
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
The MCM67Q709A is available in an 86–bump surface mount PBGA (Plastic
Ball Grid Array) package.
Single 5 V
±
5% Power Supply
Fast Cycle Time: 10 ns Max
Single Clock Operation
TTL Input and Output Levels (Outputs LVTTL Compatible)
Address, Data Input, E, W, G Registers On–Chip
100 MHz Maximum Clock Cycle Time
Self–Timed Write
Separate Data Input and Output Pins
Transparent–Write and Pass–Through
High Output Drive Capability: 50 pF/Output at Rated Access Time
Boundary Scan Implementation
86–Bump PBGA Package for High Speed Operation
Order this document
by MCM67Q709A/D
SEMICONDUCTOR TECHNICAL DATA
MCM67Q709A
A0 – A16
E
. . . . . . . . . . . . . . . . . . . . . . . . .
W
. . . . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . . . . .
D0 – D8
. . . . . . . . . . . . . . . . . . . .
Q0 – Q8
. . . . . . . . . . . . . . . . . .
K
. . . . . . . . . . . . . . . . . . . . . . . . . .
SCK
. . . . . . . . . . . . . . . . . .
SE
. . . . . . . . . . . . . . . . . . . . . . .
SDI
. . . . . . . . . . . . . . . . . . . .
SDO
. . . . . . . . . . . . . . . . .
VCC
. . . . . . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . . . . .
NC
. . . . . . . . . . . . . . . . . . . . .
Address Input
Chip Enable
Write Enable
Output Enable
Data Inputs
Data Outputs
Clock Input
Scan Clock Input
Scan Enable
Scan Data Input
Scan Data Output
+ 5 V Power Supply
. . . . . . . . . . . . . . . . .
Ground
No Connection
PIN NAMES
ZP PACKAGE
PBGA
CASE 896A–02
REV 3
8/13/99
9
8
7
6
5
4
B
C
G
A
D
E
F
H
J
Not to Scale
3
2
1
TOP VIEW
VSS
VSS
NC
A15
D7
A16
VSS
K
G
A14
VSS
Q8
VSS
VSS
VCC
VSS
SDO
SDI
VCC
W
E
A4
A0
A2
D8
A6
Q6
D6
Q4
D4
Q2
D2
D0
Q0
A1
VSS
Q7
D5
VCC
Q5
Q3
D3
VSS
D1
A12
Q1
A5
A8
A9
VSS
A10
A3
A7
SE
VCC
SCK
A11
A13
NC
VSS
VSS VSS VSS
VSS
VSS VSS VSS
VSS
VSS
VSS VSS VSS
VSS
VSS
VSS VSS VSS
VSS
VSS
VSS
VSS
VSS VSS VSS
VSS
VSS
K
PIN ASSIGNMENT
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