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參數資料
| 型號： | MCM67Q709A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 128Kx9 Bit Synchronous Fast Static RAM(128Kx9 Bit同步快速靜態存儲器) |
| 中文描述： | 128Kx9位同步快速靜態存儲器（128Kx9位同步快速靜態存儲器） |
| 文件頁數： | 9/12頁 |
| 文件大小： | 145K |
| 代理商： | MCM67Q709A |
MCM67Q709A
9
MOTOROLA FAST SRAM
BOUNDARY SCAN CYCLE TIMING
Parameter
MCM67Q709A–10
U i
Unit
Notes
Symbol
Min
Max
Cycle Time
tCHCH2
tCHCL2
tCLCH2
tSS
tBS
tSR
tCLMH
tMHCH
tCHML
tIVCH
tCHIX
tCLOV
100
—
ns
Clock High Pulse Width
40
—
ns
Clock Low Pulse Width
40
—
ns
Scan Mode Setup Time
10
—
ns
1
Bypass Mode Setup Time
10
—
ns
2
Scan Mode Recovery Time
100
—
ns
3
SCK Low to SE Hold High
10
—
ns
4
SE High to SCK High Setup
10
—
ns
5
SCK High to SE Low Hold Time
10
—
ns
6
SDI Valid to SCK High Setup
10
—
ns
SCK High to SDI Don’t Care
10
—
ns
SCK Low to SDO Valid
—
20
ns
NOTES:
1. The minimum delay required between ending normal operation and beginning scan operations.
2. The minimum delay required between ending shift mode and beginning bypass mode.
3. The minimum delay required before restarting normal RAM operation.
4. The minimum delay required before executing a parallel load operation.
5. The minimum delay required between a parallel load operation and a shift.
6. Minimum shift command hold time.
BOUNDARY SCAN
OVERVIEW
Boundary scan is a simple, non–intrusive scheme that
allows verification of electrical continuity for each of a
clocked RAMs logically active inputs and I/Os without ad-
versely affecting RAM performance. Boundary scan allows
the user to monitor the logic levels applied to each signal I/O
on the RAM, and to shift them out in a serial bit stream.
OPERATION
Boundary scan requires four signal pins for implementa-
tion: Scan Data In (SDI), Scan Data Out (SDO), Scan Clock
(SCK, active high), and Scan Enable (SE, active high).
Boundary scan provides three modes of operation: (1) nor-
mal RAM operation, (2) scan, and (3) bypass. For normal
RAM operation, SCK and SE must be held low. The RAM will
always return to normal operation immediately after the RAM
receives a rising edge of the RAM input clock (K) with SCK
and SE held low. To enter scan mode, SCK is activated. The
first rising edge of SCK is used to latch in the data on the
scan registers. SE is then driven high to disable additional in-
put data from entering the scan registers. Every falling edge
of SCK serially shifts data through the scan registers and
onto the SDO pin. To enter bypass mode simply exercise
SCK with SE held low. In this mode, SDI is sampled on the
rising edge of SCK. The level found on SDI is then driven out
on SDO on the next falling edge of SCK.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MCM67Q709AZP10 | 制造商:Motorola Inc 功能描述:Synchronous SRAM, 128K x 9, 86 Pin, Plastic, BGA |
| MCM67Q709AZP10R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 9 Bit Separate I/O Synchronous Fast Static RAM |
| MCM67Q909 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512K x 9 Bit Separate I/O Synchronous Fast Static RAM |
| MCM67Q909ZP12 | 制造商:Motorola Inc 功能描述: |
| MCM67Q909ZP12R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512K x 9 Bit Separate I/O Synchronous Fast Static RAM |
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