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參數資料
| 型號： | MCM6929AWJ10 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256K x 4 Bit Fast Static Random Access Memory |
| 中文描述： | 256K X 4 STANDARD SRAM, 10 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數： | 4/8頁 |
| 文件大小： | 119K |
| 代理商： | MCM6929AWJ10 |
MCM6929A
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to +70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
2 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
See Figure 1
READ CYCLE TIMING
(See Notes 1 and 2)
6929A–8
6929A–10
6929A–12
6929A–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
8
—
10
—
12
—
15
—
ns
3
Address Access Time
—
8
—
10
—
12
—
15
ns
Enable Access Time
—
8
—
10
—
12
—
15
ns
Output Enable Access Time
—
4
—
5
—
6
—
7
ns
Output Hold from Address Change
3
—
3
—
3
—
3
—
ns
Enable Low to Output Active
3
—
3
—
3
—
3
—
ns
4,5,6
Output Enable Low to Output Active
0
—
0
—
0
—
0
—
ns
4,5,6
Enable High to Output High–Z
—
4
—
5
—
6
—
7
ns
4,5,6
Output Enable High to Output High–Z
—
4
—
5
—
6
—
7
ns
4,5,6
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
8. Addresses valid prior to or coincident with E going low.
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a mini-
mum since the system must supply at least that much
time. On the other hand, responses from the memory
are specified from the device point of view. Thus, the
access time is shown as a maximum since the device
never provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. AC Test Load
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