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參數資料
| 型號： | MCM69C233 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4K x 64 CAM(4K x 64內容可尋址存儲器) |
| 中文描述： | 4K的× 64凸輪（4K的× 64內容可尋址存儲器） |
| 文件頁數： | 10/22頁 |
| 文件大小： | 167K |
| 代理商： | MCM69C233 |
MCM69C233
SCM69C233
10
MOTOROLA FAST SRAM
SET FAST–READ REGISTER VALUE
This operation defines the table address that is output by
the fast–read operation. The least significant 12 bits of I/O
register 0 are copied to the register.
The fast–read instruction can only be executed while the
entry queue is empty, as reflected by the queue–empty flag
being set (bit 4 of the flag register). If this operation is at-
tempted while the entry queue is not empty, the value
FFFC16 is written to the error code register, the error–condi-
tion flag (bit 7) is set in the flag register, and an interrupt is
generated if enabled by bit 7 of the interrupt register.
FAST READ
This operation is used to output the contents of one entry
in the CAM table. The fast–read register is used to specify
the appropriate entry, and is then auto–incremented. As a re-
sult, successive execution of multiple fast–read operations
will provide access to contiguous entries in the CAM table.
The CAM entry is copied to I/O registers 0 – 3, with bit 15
of register 3 as the most significant bit, and bit 0 of register 0
as the least significant bit.
The fast–read instruction can only be executed while the
entry queue is empty, as reflected by the queue–empty flag
being set (bit 4 of the flag register.) If this operation is at-
tempted while the entry queue is not empty, the value
FFFC16 is written to the error code register, the error–condi-
tion flag (bit 7) is set in the flag register, and an interrupt is
generated if enabled by bit 7 of the interrupt register.
SET ATM MODE
When the MCM69C233 is placed in ATM mode, it provides
simultaneous searching for virtual path circuits (VPCs) and
virtual connection circuits (VCCs). A VCC is detected when
both the VPI and the VCI of an incoming cell match an entry
in the CAM. A VPC match occurs when the VPI of an incom-
ing cell matches the VPI field of a CAM entry that has all 1s
as its VCI. A VPC match is signaled by the assertion of the
VPC pin along with the MS pin. At 66 MHz, a match is com-
pleted in 210 ns, whether the applied VPI/VCI belongs to a
VCC or a VPC.
The VCI match field must be defined as bits 32 – 47 of
each entry, and the VPI match data must occupy bits 48 – 59.
The VPI can be limited to bits 48 – 55, if the switch handles
only User–Network Interface (UNI) protocols. The mask reg-
ister should be used to “don’t care” any unused bits beyond
the VPI field. Entering ATM mode will set bit 9 of the flag reg-
ister.
To load a VPC into the CAM table, the desired VPI value is
written (right justified) to I/O register 3, FFFF16 is written to
I/O register 2 as the VCI field, the upper half of the desired
output word is written to I/O register 1, and the lower half of
the desired output word is written to I/O register 0. Then, the
“INSERT VALUE” instruction is written to the operation regis-
ter.
When performing a match operation, the VCI must be
placed in bits 0 – 15 of the MQ port. The VPI is expected on
bits 16 – 27, or bits 16 – 23 in the UNI case.
buffered–entry mode insertions and deletions are modified
in the following way when the MCM69C233 is in ATM mode.
If you try to add a VCC with the same VPI as an existing
VPC, you overwrite the VPC. If you try to delete a VCC when
the VCC is not in the table, but a VPC with that VPI is in the
table, the VPC will be deleted.
The CAM table should never contain, simultaneously, a
VCC entry and VPC entry with matching VPIs. Violation of
this requirement may lead to unpredictable behavior.
Bits 60 – 63 may be used for matching in ATM mode if the
application requires extra bits. The use of bits 0 – 31 for
matching is not supported in ATM mode.
MATCH CYCLE TIME
At 66 MHz, the MCM69C233 completes a match 210 ns,
or 14 clock cycles, after assertion of the SM signal. If minimal
entries need to be added to or deleted from the CAM, the part
can be cycled in 18 clocks, or 270 ns. In other words, SM can
be asserted again immediately after the completion of a
match operation and data output.
However, idle time is required between matches to allow
insertions or deletions. The worst case occurs if an entry with
a match data value smaller than any other entry in the CAM
is continually added and dropped from the table. The number
of insertion/deletion pairs per second in this scenario is
shown versus match cycle time as the curve labeled “Worst
Case” in Figure 3. As shown, a match cycle time of 270 ns
allows for 452 insertion/deletion pairs per second. Note that
this analysis is based on a 66 MHz input clock. Values should
be derated in proportion to any decrease in clock speed. For
example, at 33 MHz, twice as much idle time is required to
achieve the same number of insertion/deletion pairs per
second.
A more typical case would consist of either randomly
placed insertions and deletions in the CAM table (as deter-
mined by the magnitude of the match field), or when inser-
tions occur at one end of the table and deletions occur at the
other end. The number of insertion/deletion pairs per second
in this scenario is shown versus match cycle time as the
curve labeled “Typical” in Figure 3. As shown, a match cycle
time of 18 clocks allows for 904 insertion/deletion pairs per
second.
For any match cycle time
≥
18 clocks, the number of clock
cycles to perform a worst–case insertion ordeletion is equal
to 8192 x MCT /(MCT – 16) cycles, where MCT is the match
cycle time in clock cycles. In general, the time for an insertion
or deletion is proportional to its distance from the end of the
CAM table. That is, entries with the largest match values take
the least time to insert or delete, while entries with the small-
est values take the most time.
Therefore, the effective rate of insertion and deletion is
maximized if the longest–lived entries are placed near the
beginning of the table and the shortest–lived entries are
placed near the end of the table. For an ATM application, this
would correspond to the assignment of small VPI values to
permanent virtual circuits and large VPI values to switched
virtual circuits.
Note that at start–up, when entries are loaded into the
CAM via the fast–entry mode, the process is dominated by
the time it takes to execute the initialization instruction that
follows. The resulting effective rate of loading the CAM at
start–up is approximately 227,500 entries per second.
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