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參數(shù)資料
| 型號(hào)： | MCM69F618CTQ12R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K X 18 CACHE SRAM, 12 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 203K |
| 代理商： | MCM69F618CTQ12R |
MCM69F618C
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
1 V/ns (20% to 80%)
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
Parameter
Symbol
b l
69F618C–8.5
69F618C–9
69F618C–10
69F618C–12
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tAVKH
tADKH
tDVKH
tWVKH
tEVKH
12
—
12
—
15
—
16.6
—
ns
Clock High Pulse Width
4
—
4
—
5
—
6
—
ns
Clock Low Pulse Width
4
—
4
—
5
—
6
—
ns
Clock Access Time
—
8.5
—
9
—
10
—
12
ns
Output Enable to Output Valid
—
5
—
5
—
5
—
6
ns
Clock High to Output Active
0
—
0
—
0
—
0
—
ns
4
Clock High to Output Change
3
—
3
—
3
—
3
—
ns
4
Output Enable to Output Active
0
—
0
—
0
—
0
—
ns
4
Output Disable to Q High–Z
—
5
—
5
—
5
—
6
ns
4, 5
Clock High to Q High–Z
2.5
5
3
5
3
5
3
6
ns
4, 5
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
2.5
—
2.5
—
2.5
—
2.5
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. This parameter is sampled and not 100% tested.
5. Measured at
±
200 mV from steady state.
OUTPUT
Z0 = 50
RL = 50
VT = 1.5 V
Figure 1. AC Test Load
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