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參數資料
| 型號： | MCM69F618CTQ9R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K X 18 CACHE SRAM, 9 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 203K |
| 代理商： | MCM69F618CTQ9R |
MCM69F618C
1
MOTOROLA FAST SRAM
Motorola, Inc. 1998
64K x 18 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
The MCM69F618C is a 1M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC
, 486, i960
, and Pentium
microprocessors. It is organized as 64K
words of 18 bits each. This device integrates input registers, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). BiCMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69F618C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and syn-
chronous write enable SW are provided to allow writes to either individual bytes
or to both bytes. The two bytes are designated as “a” and “b”. SBa controls DQa
and SBb controls DQb. Individual bytes are written if the selected byte writes SBx
are asserted with SW. Both bytes are written if either SGW is asserted or if all SBx
and SW are asserted.
For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array.
The MCM69F618C operates from a 3.3 V power supply and all inputs and
outputs are LVTTL compatible and 5 V tolerant.
MCM69F618C–8.5 = 8.5 ns Access / 12 ns Cycle
MCM69F618C–9 = 9 ns Access / 12 ns Cycle
MCM69F618C–10 = 10 ns Access / 15 ns Cycle
MCM69F618C–12= 12 ns Access / 16.6 ns Cycle
Single 3.3 V + 10%, – 5% Power Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
5 V Tolerant on all Pins (Inputs and I/Os)
100–Pin TQFP Package
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.
Order this document
by MCM69F618C/D
SEMICONDUCTOR TECHNICAL DATA
MCM69F618C
TQ PACKAGE
TQFP
CASE 983A–01
REV 2
2/18/98
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