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參數(shù)資料
| 型號(hào)： | MCM69F618CTQ9R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K X 18 CACHE SRAM, 9 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 203K |
| 代理商： | MCM69F618CTQ9R |
MCM69F618C
4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADSC
Input
Synchronous Address Status Controller: Initiates READ, WRITE or chip
deselect cycle.
84
ADSP
Input
Synchronous Address Status Processor: Initiates READ, WRITE or
chip deselect cycle (exception — chip deselect does not occur when
ADSP is asserted and SE1 is high).
83
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
DQx
I/O
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
86
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
89
K
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 80, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1,SA0
Input
Synchronous Address Inputs: these pins must be wired to the two LSBs
of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high–blocks ADSP or deselects chip when ADSC is asserted.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
4, 11, 15, 20, 27, 41, 54,
61, 65, 70, 77, 91
VDD
Supply
Power Supply: 3.3 V + 10%, – 5%.
5, 10, 17, 21, 26, 40, 55,
60, 67, 71, 76, 90
VSS
Supply
Ground.
64
NC
Input
No Connection: There is no connection to the chip. For compatibility
reasons, it is recommended that this pin be tied low for system designs
that do not have a sleep mode associated with the cache/memory
controller. Other vendors’ RAMs may have implemented this Sleep
Mode (ZZ) feature.
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,
38, 39, 42, 43, 49, 50, 51, 52,
53, 56, 57, 66, 75, 78, 79, 95, 96
NC
—
No Connection: There is no connection to the chip.
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