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參數資料
型號： MCP18480T-I/SS
廠商： Microchip Technology
文件頁數： 46/64頁
文件大小： 871K
描述： IC HOT SWAP CTRLR -48V 20SSOP
標準包裝： 1,600
類型： 熱交換控制器
應用： IP 電話，LAN 網絡供電，網絡路由器和交換機
內部開關： 無
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應商設備封裝： 20-SSOP
包裝： 帶卷 (TR)
MCP18480
DS20091B-page 46
?2003 Microchip Technology Inc.
6.8.4
CURRENT LIMIT BLOCK
An excessive current flowing through the external FET
is sensed as a voltage across an external resistor
connected between the FETs source and V
NEG
.
The drain voltage is sensed with a resistor divider net-
work, as shown in Figure 4-1 and Figure 4-2. The volt-
age tap is applied to a circuit whose output is 50 mV
above V
NEG
 when the drain of the external FET is at
V
NEG
. The output is 12 mV when the V
FB
  pin is
e V
NEG
+0.5V. This output voltage is the Current Limit
Feedback (CLFB) signal to the gate driver block for use
in the fold-back current-limiting.
The CLFB voltage serves as the reference for a com-
parator whose other input monitors the voltage across
the current limit sense resistor in series with the source
of the external FET. When the SENSE pin exceeds the
voltage on CLFB, a comparator output goes high to
start the timer (see Section 6.8.5). The V
DS
 dependent
threshold for the current limit helps keep the FET within
its safe operating area.
Another   comparator   in   the   current-limiting   block
watches the SENSE pin for potentially catastrophic
over-current conditions, which require immediate ter-
mination of conduction in the pass MOSFET. The out-
put of this comparator trips a comparator used in the
TIMER block to skip the first part of the timeout cycle
and go straight to the off period. In some cases, the
user may want to program the system to shut off imme-
diately if there is a short-circuit condition that exceeds
a desired level. To use this feature, connect a divider
between the V
REFIN
 pin and the V
NEG
 pin, with its cen-
tertap at the CL input pin. The circuit breaker current
that would trigger this mode is given by Equation 6-5.
EQUATION 6-5:    CIRCUIT BREAKER
THRESHOLD
If this function is not needed in a particular application,
it can be disabled by connecting the CL pin to the
V
REFIN
 pin. Equation 6-6 shows the current of the CL
pin during current-limiting.
EQUATION 6-6:    CL PIN CURRENT
6.8.5
TIMER BLOCK
Since the external FET can survive brief over-current
episodes, it is unnecessary to turn off the FET instantly
when the current rises too high (see external FET data
sheet). The timer circuit uses the output of the compar-
ator in the current-limiting block to begin charging an
external capacitor with 16 " I
RISET
  (typically 160 礎)
when an over-current condition is detected. When the
voltage on the capacitor ramps up to 1.25V, a compar-
ator output goes high. This output goes to another
block that tells the gate driver to turn the external FET
off and deassert the PWRGOOD pin. The complemen-
tary output of the timer changes the state of a hystere-
sis circuit that drops the reference input of the
comparator to V
NEG
 + 100 mV (?10 mV).
When the FET is off, the current through it drops to
zero, so that the voltage across the current sense resis-
tor also goes to zero and the current limit signal to the
timer block goes away. The timer capacitor starts to
discharge at a rate set by the external resistor, R
DISCH
.
Equation 6-7 shows the equations used to calculate the
current at the TIMER pin. This current is used for other
calculations.
EQUATION 6-7:    TIMER PIN CURRENT
CALCULATIONS
The delay between the inception of the over-current
condition and the deactivation of the FET is given by
Equation 6-8.
EQUATION 6-8:    OVER-CURRENT FAULT
DELAY
The time required to reset the timer and reactivate the
gate driver is given by Equation 6-9.
EQUATION 6-9:    OVER-CURRENT
REACTIVATION DELAY
As described above, the timer circuit operates as a
free-running, multi-vibrator, if RESTART
 is low.
I
CAT
V
REFIN
R
CL1
R
CL2
+
-- - - -- - - - -- - - -- - - -- - - -- - - - -- - - -
?/DIV>
?/DIV>
?/DIV>
?/DIV>
R
CL2
"
R
SENSE
- - - - -- - - -- - - -- - - -- - - - -- - - -- - - -- - - -- - - - -- - - -- - - -- - - -- - - -
=
0V
> 0.5V
50 mV
12 mV
V
SENSE
for V
FB
 > 0.5V, V
SENSE
 = 0.012V 
I
CL
V
SENSE
R
SENSE
- - - -- - - -- - - -- - - -- -
=
V
SENSE
0.76
0.05V
V
DS
R
FB2
?/DIV>
R
FB1
R
FB2
+
- - -- - - -- - - -- - - -- - - - -- - - -- - - -- - -

?/DIV>
?/DIV>
?/DIV>
?/DIV>
0.012V
+
?/DIV>
=
Legend: I
RISET
 is the current through the external
R
ISET
 resistor
I
TIMER
16   I
RISET
"
=
Typical
I
TIMER
10   I
RISET
"
=
Minimum
I
TIMER
20   I
RISET
"
=
Maximum
T
CLD1
C
TIMER
I
TIMER
- - - -- - - - -- - - -- - - -- -   1.25
"
=
T
CLD2
9.2   C
TIMER
"
R
DISCH
"
=
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