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參數資料
型號： MIC2086-MBQS TR
廠商： Micrel Inc
文件頁數： 16/29頁
文件大小： 1008K
描述： IC CTRLR HOW SWAP SGL 20-QSOP
標準包裝： 2,500
類型： 熱交換控制器
應用： 通用型 Infiniband?
內部開關： 無
電源電壓： 2.3 V ~ 16.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.154"，3.90mm 寬）
供應商設備封裝： 20-QSOP
包裝： 帶卷 (TR)
其它名稱： MIC2086-MBQSTR
MIC2086-MBQSTR-ND
Micrel, Inc.
MIC2085/2086
 
 
May 2006 
16
M9999-050406
(408) 955-1690
 
connected to CPOR sets the interval, t
POR
, and t
POR
 is
equivalent to the start-up delay, t
START
 (see Equation 1).
A capacitor connected to CFILTER is used to set the
timer   which   activates   the   circuit   breaker   during
overcurrent conditions. When the voltage across the
sense resistor exceeds the slow trip current limit
threshold of 48mV, the overcurrent timer begins to
charge for a period, t
OCSLOW
, determined by CFILTER. If
no capacitor is used at CFILTER, then t
OCSLOW
 defaults
to 5祍. If t
OCSLOW
  elapses, then the circuit breaker is
activated and the GATE output is immediately pulled to
ground. The following equation is used to determine the
overcurrent timer period, t
OCSLOW
.
(  )
礔
C
0.062
I
V
C
t
FILTER
TIMER
TH
FILTER
OCSLOW
?/DIV>
E
?/DIV>
=
  (7)
where V
TH
, the CFILTER timer threshold, is 1.24V and
I
TIMER
, the overcurrent timer current, is 20礎. Tables 2
and 3 provide a quick reference for several timer
calculations using select standard value capacitors.
C
POR
 
t
POR
 = t
START
 
0.01礔
6ms
0.02礔
12ms
0.033礔
18.5ms
0.05礔
30ms
0.1礔
60ms
0.33礔
200ms
Table 2. Selected Power-On Reset and
Start-Up Delays
C
FILTER
 
t
OCSLOW
 
1800pF
100祍
4700pF
290祍
8200pF
500祍
0.01礔
620祍
0.02礔
1.2ms
0.033礔
2.0ms
0.05礔
3.0ms
0.1礔
6.2ms
0.33礔
20.7ms
Table 3. Selected Overcurrent Timer Delays
Application Information
Output Undervoltage Detection
For output undervoltage detection, the first consideration
is to establish the output voltage level that indicates
power is good. For this example, the output value for
which a 12V supply will signal good is 11V. Next,
consider the tolerances of the input supply and FB
threshold (VFB). For this example, the 12V supply varies
?%, thus the resulting output voltage may be as low as
11.4V and as high as 12.6V. Additionally, the FB
threshold has ?0mV tolerance and may be as low
as1.19V and as high as 1.29V. Thus, to determine the
values of the resistive divider network (R5 and R6) at the
FB pin, shown in Figure 5, use the following iterative
design procedure.
1)   Choose R6 so as to limit the current through the
divider to approximately 100礎 or less.
 
12.9k&
100?/DIV>
1.29V
100?/DIV>
V
R6
(MAX)
FB
e
?/DIV>
e
?/DIV>
e
 
R6 is chosen as 13.3k& ?1%
2)   Next, determine R5 using the output good
voltage of 11V and the following equation:
 
(
)
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
+
=
R6
R6
R5
V
V
FB
OUT(Good)
  (8)
Using some basic algebra and simplifying Equation 8 to
isolate R5, yields:
 
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>

?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
1
V
V
R6
R5
FB(MAX)
OUT(Good)
  (8.1)
where V
FB(MAX)
  = 1.29V, V
OUT(Good)
  = 11V, and R6
is13.3k&. Substituting these values into Equation 8.1
now yields R5 = 100.11k&. A standard 100k& ?1% is
selected. Now, consider the 11.4V minimum output
voltage, the lower tolerance for R6 and higher tolerance
for R5, 13.17k& and101k&, respectively. With only
11.4V available, the voltage sensed at the FB pin
exceeds   V
FB(MAX)
,   thus   the   /POR   and   PWRGD
(MIC2086) signals will transition from LOW to HIGH,
indicating power is good given the worse case
tolerances of this example.
Input Overvoltage Protection
The external CRWBR circuit shown in Figure 5 consists
of capacitor C4, resistor R7, NPN transistor Q2, and
SCR Q3.The capacitor establishes a time duration for an
overvoltage condition to last before the circuit breaker
trips. The CRWBR timer duration is approximated by the
following equation:
 
)
(  )
礔
C4
0.01
I
V
C4
t
CR
CR
OVCR
?/DIV>
E
E
  (9)
where V
CR
, the CRWBR pin threshold, is 0.47V and I
CR
,
the CRWBR pin current, is 45礎 during the timer period
(see the CRWBR timer pin description for further
description). A similar design approach as the previous
undervoltage detection example is recommended for the
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