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參數(shù)資料
型號(hào): MIC2583R-MBQS TR
廠商: Micrel Inc
文件頁(yè)數(shù): 14/25頁(yè)
文件大小: 826K
描述: IC CTRLR HOT SWAP 200MV 16-QSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開(kāi)關(guān): 無(wú)
電源電壓: 2.3 V ~ 13.2 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
其它名稱: MIC2583R-MBQSTR
MIC2583R-MBQSTR-ND
Micrel, Inc.
MIC2582/MIC2583
 
 
April 2009 
14
M9999-043009-C
 
following equation:
  Output Voltage Slew Rate, dV
OUT
/dt =
LOAD
LIM
C
I
  (4)
where I
LIM
  is the programmed current limit value.
Consequently, the value of C
FILTER
 must be selected to
ensure that the overcurrent response time, t
OCSLOW
,
exceeds the time needed for the output to reach its final
value. For example, given a MOSFET with an input
capacitance C
ISS
  = C
GATE
  = 4700pF, C
LOAD
  is 2200礔,
and I
LIM
  is set to 6A with a 12V input, then the load
capacitance dominates as determined by the calculated
INRUSH > I
LIM
. Therefore, the output voltage slew rate
determined from Equation 4 is:
Output Voltage Slew Rate, dV
OUT
/dt =
ms
V
F
A
73
.
2
2200
6
=
?/DIV>
 
and the resulting t
OCSLOW
  needed to achieve a 12V
output is approximately 4.5ms. (See Power-On Reset
and Overcurrent Timer Delays section to calculate
t
OCSLOW
).
GATE Capacitance Dominated Start-Up
In this case, the value of the load capacitance relative to
the GATE capacitance is small enough such that the
load current during start-up never exceeds the current
limit threshold as determined by Equation 3. The
minimum value of C
GATE
 that will ensure that the current
limit is never exceeded is given by the equation below:
 
LOAD
LIM
GATE
GATE
C
I
I
C
?/DIV>
=
(min)
  (5)
where C
GATE
  is the summation of the MOSFET input
capacitance   (C
ISS
)   and   the   value   of   the   external
capacitor connected to the GATE pin of the MIC2582/83
to ground. Once C
GATE
 is determined, use the following
equation to determine the output slew rate for gate
capacitance dominated start-up.
  dV
OUT
/dt =
GATE
GATE
C
I
  (6)
Table 1 depicts the output slew rate for various values of
C
GATE
.
I
GATE
 = 17礎(chǔ)
C
GATE
 
dV
OUT
/dt
0.001礔
17V/ms
0.01礔
1.7V/ms
0.1礔
0.17V/ms
1礔
0.017V/ms
Table 1. Output Slew Rate Selection for GATE
Capacitance Dominated Start-Up
Current Limiting and Dual-Level Circuit Breaker
Many applications will require that the inrush and steady
state supply current be limited at a specific value in order
to   protect   critical   components   within   the   system.
Connecting a sense resistor between the VCC and
SENSE pins sets the nominal current limit value of the
MIC2582/83 and the current limit is calculated using
Equation 2.
The MIC2582/83 also features a dual-level circuit
breaker triggered via 50mV and 100mV current-limit
thresholds sensed across the VCC and SENSE pins.
The first level of the circuit breaker functions as follows.
For the MIC2583/83R, once the voltage sensed across
these two pins exceeds 50mV, the overcurrent timer, its
duration set by capacitor C
FILTER
, starts to ramp the
voltage at C
FILTER
 using a 6.5礎(chǔ) constant current source.
If the voltage at C
FILTER
  reaches the overcurrent timer
threshold (V
TH
) of 1.24V, then C
FILTER
  immediately
returns to ground as the circuit breaker trips and the
GATE output is immediately shut down. The default
overcurrent time period for the MIC2582/83 is 5祍. For
the second level, if the voltage sensed across VCC and
SENSE exceeds 100mV at any time, the circuit breaker
trips and the GATE shuts down immediately, bypassing
the overcurrent time period. The MIC2582-MYM option
is equipped with only a single circuit breaker threshold
(50mV). To disable current limit and circuit breaker
operation, tie the SENSE and VCC pins together and the
C
FILTER
 (MIC2583/83R) pin to ground.
Output Undervoltage Detection
The MIC2582/83 employ output undervoltage detection
by monitoring the output voltage through a resistive
divider connected at the FB pin. During turn on, while the
voltage at the FB pin is below the threshold (V
FB
), the
/POR pin is asserted low.
Once the FB pin voltage crosses V
FB
, a 2.5礎(chǔ) current
source charges capacitor C
POR
. Once the CPOR pin
voltage reaches 1.24V, the time period t
POR
 elapses as
the CPOR pin is pulled to ground and the /POR pin goes
HIGH. If the voltage at FB drops below V
FB
 for more than
10祍, the /POR pin resets for at least one timing cycle
defined by t
POR
  (See Applications Information for an
example).
Power-On Reset and Overcurrent Timer Delays
The Power-On Reset delay, t
POR
, is the time period for
the /POR pin to go HIGH once the voltage at the FB pin
exceeds the power-good threshold (V
FB
). A capacitor
connected to CPOR sets the interval and is determined
by using Equation 1 with V
TH
 substituted for V
START
. The
resulting equation becomes:
 
(   )
F
C
I
V
C
t
POR
CPOR
TH
POR
POR
?/DIV>
?/DIV>
E
?/DIV>
=
5
.
0
  (7)
where the Power-On Reset threshold (V
TH
) and timer
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