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參數資料
| 型號： | MIC2583R-MBQS TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 3/25頁 |
| 文件大小： | 826K |
| 描述： | IC CTRLR HOT SWAP 200MV 16-QSOP |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 2.3 V ~ 13.2 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2583R-MBQSTR MIC2583R-MBQSTR-ND |
Micrel, Inc.
MIC2582/MIC2583
April 2009
3
M9999-043009-C
Pin Description
Pin Number
8-Pin SOIC
Pin Number
16-Pin QSOP
Pin Name
Pin Name
1
1
/POR
Power-On Reset Output: Open drain N-channel device, Active Low. This pin
remains asserted during start-up until a time period (t
POR
) after the FB pin
voltage rises above the power-good threshold (VFB). The timing capacitor C
POR
determines t
POR
. When the output voltage monitored at the FB pin falls below
V
FB
, /POR is asserted for a minimum of one timing cycle (t
POR
). The /POR pin
requires a pull-up resistor (10k& minimum) to VCC.
2
3
ON
ON Input: Active High. The ON pin, an input to a Schmitt-triggered comparator
used to enable/disable the controller, is compared to a 1.24V reference with
50mV of hysteresis. When a logic high is applied to the ON pin (V
ON
> 1.24V), a
start-up sequence begins when the GATE pin starts ramping up towards its final
operating voltage. When the ON pin receives a logic low signal (V
ON
< 1.19V),
the GATE pin is grounded and /FAULT remains high if VCC is above the UVLO
threshold. ON must be low for 20祍 in order to initiate a start-up sequence.
Additionally, toggling the ON pin LOW to HIGH resets the circuit breaker.
3
4
CPOR
Power-On Reset Timer: A capacitor connected between this pin and ground sets
the supply contact start-up delay (t
START
) and the power-on reset interval (t
POR
).
When VCC rises above the UVLO threshold, the capacitor connected to C
POR
begins to charge. When the voltage at CPOR crosses 0.3V, the start-up
threshold (V
START
), a start cycle is initiated if ON is asserted while capacitor C
POR
is immediately discharged to ground. When the voltage at FB rises above V
FB
,
capacitor C
POR
begins to charge again. When the voltage at CPOR rises above
the power-on reset delay threshold (V
TH
), the timer resets by pulling CPOR to
ground, and /POR is de-asserted. If C
POR
is left open, then t
START
defaults to
20祍.
4
7, 8
GND
Ground Connection: Tie to analog ground.
5
12
FB
Power-Good Threshold Input (Under-voltage Detect): This input is internally
compared to a 1.24V reference with 30mV of hysteresis. An external resistive
divider may be used to set the voltage at this pin. If this input momentarily goes
below 1.24V, then /POR is activated for one timing cycle, t
POR
, indicating an
output under-voltage condition. The /POR signal de-asserts one timing cycle
after the FB pin exceeds the power-good threshold by 30mV. A 5祍 filter on this
pin prevents glitches from inadvertently activating this signal.
6
14
GATE
Gate Drive Output: Connects to the gate of an external N-channel MOSFET. An
internal clamp ensures that no more than 9V is applied between the GATE pin
and the source of the external MOSFET. The GATE pin is immediately brought
low when either the circuit breaker trips or an under-voltage lockout condition
occurs.
7
15
SENSE
Circuit Breaker Sense Input: A resistor between this pin and VCC sets the
current limit threshold. Whenever the voltage across the sense resistor exceeds
the slow trip current limit threshold (V
TRIPSLOW
), the GATE voltage is adjusted to
ensure a constant load current. If V
TRIPSLOW
(50mV) is exceeded for longer than
time period t
OCSLOW
, then the circuit breaker is tripped and the GATE pin is
immediately pulled low. If the voltage across the sense resistor exceeds the fast
trip circuit breaker threshold, V
TRIPFAST
, at any point due to fast, high amplitude
power supply faults, then the GATE pin is immediately brought low without delay.
To disable the circuit breaker, the SENSE and VCC pins can be tied together.
The default V
TRIPFAST
for either device is 100mV. Other fast trip thresholds are
available: 150mV, 200mV, or OFF (V
TRIPFAST
disabled). Please contact factory for
availability of other options.
8
16
VCC
Positive Supply Input: 2.3V to 13.2V. The GATE pin is held low by an internal
under-voltage lockout circuit until VCC exceeds a threshold of 2.2V. If VCC
exceeds 13.2V, an internal shunt regulator protects the chip from transient
voltages up to 20V at the VCC and SENSE pins.
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